Static random access memory (SRAM) tracking cells and methods of forming the same
First Claim
1. A static random access memory (SRAM) array comprising:
- a writable SRAM cell in a first row of the SRAM array;
a first SRAM tracking cell in the first row of the SRAM array, the first SRAM tracking cell comprising;
a first pair of cross coupled invertors;
a first transistor comprising;
a first gate electrically connected to an output of the first pair of cross coupled invertors;
a first source/drain; and
a second source/drain; and
a second transistor comprising;
a second gate electrically connected to a first ground line, wherein a voltage applied to the second gate is directly tied to a voltage of the first ground line;
a third source/drain electrically connected to the first source/drain; and
a fourth source/drain electrically connected to a read tracking bit line (BL),wherein the read tracking BL is electrically connected to a read sense amplifier (SA) timing control circuit.
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Abstract
An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.
18 Citations
20 Claims
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1. A static random access memory (SRAM) array comprising:
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a writable SRAM cell in a first row of the SRAM array; a first SRAM tracking cell in the first row of the SRAM array, the first SRAM tracking cell comprising; a first pair of cross coupled invertors; a first transistor comprising; a first gate electrically connected to an output of the first pair of cross coupled invertors; a first source/drain; and a second source/drain; and a second transistor comprising; a second gate electrically connected to a first ground line, wherein a voltage applied to the second gate is directly tied to a voltage of the first ground line; a third source/drain electrically connected to the first source/drain; and a fourth source/drain electrically connected to a read tracking bit line (BL), wherein the read tracking BL is electrically connected to a read sense amplifier (SA) timing control circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A static random access memory (SRAM) tracking cell comprising:
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a first invertor comprising a first transistor and a second transistor sharing a first gate electrode; a third transistor sharing the first gate electrode with the first transistor and the second transistor, the third transistor comprising; a first source/drain electrically connected to a ground line; and a second source/drain; a fourth transistor having a second gate electrode, the fourth transistor comprising; a third source/drain, the second source/drain and the third source/drain being disposed between the first gate electrode and the second gate electrode; and a fourth source/drain; a first gate contact electrically connecting the first gate electrode to a power supply line; and a first source/drain contact electrically connecting the fourth source/drain to a tracking bit line (BL), wherein the tracking BL is electrically connected to a read sense amplifier (SA) timing control circuit. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method comprising:
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applying a positive supply voltage to a tracking bit line (BL), wherein the tracking BL is electrically connected to a read port of a static random access memory (SRAM) tracking cell, the SRAM tracking cell being disposed in a same row of an SRAM array as and having a different layout than a writable SRAM cell; determining a discharge time of the tracking BL, wherein the discharge time of the tracking BL is an amount of time taken, by the tracking BL, to discharge from the positive supply voltage to ground through the read port; and adjusting a clock cycle of a read sense amplifier (SA) in accordance with the discharge time of the tracking BL, wherein the read SA is electrically connected to a read bit line (RBL) of the writable SRAM cell. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification