System and method for atomic persistence in storage class memory

• US 10,163,510 B1
• Filed: 08/11/2014
• Issued: 12/25/2018
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Ellis Robinson Giles, Peter Joseph Varman
• Original Assignee: Ellis Robinson Giles, Peter Joseph Varman
• Inventors: Giles, Ellis Robinson, Varman, Peter Joseph
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): Chang, Tian-Pong
• Application Number:
  US14/457,113
• Time in Patent Office: 1,597 Days
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material

Abstract

Emerging byte-addressable persistent memory technologies, generically referred to as Storage Class Memory, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Unifying storage and memory into a memory tier that can be accessed directly requires additional burden to ensure that groups of memory operations to persistent or nonvolatile memory locations are performed sequentially, atomically, and not caught in the cache hierarchy.

The present invention provides a lightweight solution for the atomicity and durability of write operations to nonvolatile memory, while simultaneously supporting fast paths through the cache hierarchy to memory. The invention includes a hardware-supported solution with modifications to the memory hierarchy comprising a victim cache and additional memory controller logic. The invention also includes a software only method and system that provides atomic persistence to nonvolatile memory using a software alias in DRAM and log in nonvolatile memory.

Claims

1. A method for performing a group of processor load and store instructions to Storage Class Memory atomically and asynchronously, the method comprising:

creating an alias table in Dynamic Random Access Memory which catches spurious cache evictions from write-back caching of aliased Storage Class Memory addresses from corrupting a Storage Class Memory structure on a system failure;

creating a log area in a Storage Class Memory for asynchronous logging operations;

upon receiving a request for a new atomic group of processor load and store instructions to Storage Class Memory, creating a log for stored values in the group;

upon receiving a store request to a Storage Class Memory address in an atomic group of processor load and store instructions to Storage Class Memory;

asynchronously storing the Storage Class Memory address and value to be stored to the log;

determining whether an alias for the Storage Class Memory address exists;

upon determining that the alias address exists, performing a store of the value to the alias address location;

and upon determining that the alias address does not exist, storing the value to an alias address memory location in Dynamic Random Access Memory and associating the alias address with the Storage Class Memory address;

upon receiving a load request to a Storage Class Memory address in an atomic group of processor load and store instructions to Storage Class Memory;

determining whether an alias for the Storage Class Memory address exists;

upon determining that the alias address exists, returning the value in the alias address location;

and upon determining that the alias address does not exist, returning the value in the Storage Class Memory location;

upon receiving a close request for an atomic group of processor load and store instructions to Storage Class Memory, marking the log structure in Storage Class Memory as closed;

upon receiving an abort request for an atomic group of processor load and store instructions to Storage Class Memory, deleting the log for the group, performing a memory fence, notifying a log manager to copy values from completed logs to Storage Class Memory, and clearing the alias table;

and upon determining the alias table in Dynamic Random Access Memory running out of space, suspending new atomic group requests, notifying the log manager to process completed logs, and clearing the alias table.

2. The method of claim 1 where the alias table is implemented using a hash table with fine-grained locking.

3. The method of claim 1 where the alias table is implemented using a lock-free data structure.

4. The method of claim 1 wherein the memory store to the log is performed using a streaming store operation.

5. The method of claim 1 upon receiving a close request for an atomic group of processor load and store instructions to Storage Class Memory further comprising notifying a log manager to process the log.

6. The method of claim 5 wherein the log manager marks the log for a completed atomic group of processor load and store instructions to Storage Class Memory deleted after issuing a memory fence and the values for the corresponding completed store instructions are copied from the completed log to the Storage Class Memory locations.

7. The method of claim 1 wherein the log manager processes the completed logs for atomic groups of processor load and store instructions to Storage Class Memory with values in the alias table by issuing a memory fence, copying all values from the alias Dynamic Random Access Memory location to the Storage Class Memory locations, and marking the logs as deleted.

8. The method of claim 1 upon receiving a request for a new atomic group of processor load and store instructions to Storage Class Memory further comprising using a token to associate Storage Class Memory stores into an atomic group.

9. The method of claim 1 upon receiving a request for a new atomic group of processor load and store instructions to Storage Class Memory further comprising using a counter in Thread Local Storage to group nested groups of atomic Storage Class Memory loads and stores into a single atomic group of Storage Class Memory loads and stores.

10. A system for performing a group of processor load and store instructions to Storage Class Memory atomically and asynchronously, the system comprising:

one or more central processing units;

one or more levels of write-back cache hierarchy;

Dynamic Random Access Memory;

an alias table in Dynamic Random Access Memory which catches spurious cache evictions to the write-back memory hierarchy of aliased Storage Class Memory addresses from corrupting a Storage Class Memory structure on a system failure;

Storage Class Memory attached to the main-memory bus fronted by the write-back cache hierarchy;

an area of Storage Class Memory used for log operations;

a persistent atomicity memory control manager which opens a log on new atomic group requests, checks the alias table on Storage Class Memory load requests and returns the alias if exists or the original memory value, updates an alias table entry on a Storage Class Memory store request associating the address and value in the alias table and adding the address value pair to the log, and on close requests, marks the log closed, and notifies a log manager;

and a log manager which, upon receiving a log completion request, processes the log asynchronously by issuing a store fence and copying values from the completed log to the Storage Class Memory addresses for each of the entries in the log, and when running out of space in the alias table, processes completed logs and clears the alias table.

11. The system of claim 10 wherein the persistent atomicity memory control manager performs log write operations asynchronously.