Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read
First Claim
1. A semiconductor memory device comprising:
- a memory cell array including first memory cells, second memory cells and third memory cells;
a first word line connected to gates of the first memory cells;
a second word line connected to gates of the second memory cells;
a third word line connected to gates of the third memory cells; and
a control circuit configured to execute a first read operation in response to a first command set, a second read operation in response to a second command set following the first command set, and a third read operation in response to a third command set following the first command set, whereinthe first read operation includes a first read sequence, in which the control circuit applies at least first to third voltages which are different from each other, to the first word line,in the second read operation, the control circuit reads data from the second memory cells by applying a first read voltage that is set based on the result of the first read sequence of the first read operation, to the second word line, andin the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
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Abstract
A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
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Citations
17 Claims
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1. A semiconductor memory device comprising:
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a memory cell array including first memory cells, second memory cells and third memory cells; a first word line connected to gates of the first memory cells; a second word line connected to gates of the second memory cells; a third word line connected to gates of the third memory cells; and a control circuit configured to execute a first read operation in response to a first command set, a second read operation in response to a second command set following the first command set, and a third read operation in response to a third command set following the first command set, wherein the first read operation includes a first read sequence, in which the control circuit applies at least first to third voltages which are different from each other, to the first word line, in the second read operation, the control circuit reads data from the second memory cells by applying a first read voltage that is set based on the result of the first read sequence of the first read operation, to the second word line, and in the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory device comprising:
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a memory cell array including first memory cells, second memory cells, third memory cells and fourth memory cells; a first word line connected to gates of the first memory cells; a second word line connected to gates of the second memory cells; a third word line connected to gates of the third memory cells; a fourth word line connected to gates of the fourth memory cells; and a control circuit is configured to execute a first read operation in response to a first command set, a second read operation in response to a second command set following the first command set, a third read operation in response to a third command set following the second command set and a fourth read operation in response to a fourth command set following the third command set;
whereinthe first read operation includes a first read sequence, in which the control circuit applies at least first to third voltages which are different from each other, to the first word line, in the second read operation, the control circuit reads data from the second memory cells by applying a first read voltage, to the second word line, the third read operation includes a third read sequence, in which the control circuit applies at least fourth to sixth voltages which are different from each other, to the third word line, and in the fourth read operation, the control circuit reads data from the fourth memory cells by applying a second read voltage, to the fourth word line, wherein the second command set and the fourth command set each include a special command and a read command that is to be read by the control circuit prior to reading address information also included in the respective second or fourth command set, and the first read voltage is different from the second read voltage. - View Dependent Claims (10, 11, 12, 13)
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14. A method of performing a read operation in a semiconductor memory device comprising a memory cell array including first memory cells, second memory cells and third memory cells, a first word line connected to gates of the first memory cells, a second word line connected to gates of the second memory cells, and a third word line connected to gates of the third memory cells, said method comprising:
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in response to a first command set, executing a first read sequence during which at least first to third voltages which are different from each other are applied to the first word line; in response to a second command set following the first command set, reading data from the second memory cells by applying a first read voltage that is set based on the result of the first read sequence, to the second word line; and in response to a third command set following the first command set, reading data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line. - View Dependent Claims (15, 16, 17)
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Specification