Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor

• US 10,163,524 B2
• Filed: 06/20/2017
• Issued: 12/25/2018
• Est. Priority Date: 06/22/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Nguyen, Hien
• Application Number:
  US15/628,593
• Publication Number:
  US 20170372794A1
• Time in Patent Office: 553 Days
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 : Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation.

Claims

1. A semiconductor device that has a normal mode of operation and a test mode of operation, comprising:

a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level;

the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation.

2. The semiconductor device of claim 1, further including:

the at least one assist signal includes a read assist signal.

3. The semiconductor device of claim 2, further including:

a word line voltage circuit coupled to receive the read assist signal, the word line voltage circuit provides a word line potential that is substantially less than a first power supply potential in response to the read assist signal having the assist enable logic level and provides a word line potential that is essentially the same potential as the first power supply potential when the read assist signal has the assist disable logic level, wherein the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the read operation.

4. The semiconductor device of claim 2, further including:

a sense amplifier circuit coupled to receive data from the SRAM cell during a read operation and provide a data output signal, the sense amplifier circuit includes a threshold voltage compensation circuit that provides compensation for differences in threshold voltages in a first insulated gate field effect transistor (IGFET) and a second IGFET of the sense amplifier circuit during the read operation of data from the SRAM cell, wherein

the read assist signal enables the threshold voltage compensation circuit when the read assist signal has the assist enable logic level and disables the threshold voltage compensation circuit when the read assist signal has the assist disable logic level.

5. The semiconductor device of claim 1, wherein:

the at least one assist signal includes a write assist signal.

6. The semiconductor device of claim 5, further including:

a write voltage selection circuit coupled to receive the write assist signal and provide a write potential; and

a write driver circuit coupled to receive the write potential and drive a first bit line connected to the SRAM cell essentially to the write potential during a write operation, wherein

a first power supply potential provides an upper power rail to the semiconductor device and a reference potential provides a lower power rail to the semiconductor device and the write voltage selection circuit provides a write potential that is substantially less than the reference potential when the write assist signal has the assist enable logic level and provides a write potential that is essentially the reference potential when the write assist signal has the assist disable logic level.

7. The semiconductor device of claim 5, wherein:

a word line voltage circuit coupled to receive the write assist signal and provide a word line potential, wherein

the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the write operation and the word line voltage circuit provides a word line potential that is substantially greater than a first power supply potential when the write assist signal has the assist enable logic level and provides a word line potential that is essentially the first power supply potential when the write assist signal has the assist disable logic level.

8. The semiconductor device of claim 5, further including:

an array cell voltage circuit coupled to receive the write assist signal and provide a cell power supply potential, wherein

the SRAM cell is coupled to receive and is powered by the cell power supply potential and the array cell voltage circuit provides a cell power supply potential that is substantially less than a first power supply potential when the write assist signal has the assist enable logic level and provides a cell power supply potential that is essentially the first power supply potential when the write assist signal has assist disable logic level.

9. The semiconductor device of claim 1, further including:

the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by a first power supply potential, the SRAM circuit portion includes the SRAM cell.

10. A semiconductor device powered by a first power supply potential, comprising:

the semiconductor device has a normal mode of operation and a test mode of operation; and

a first circuit that generates at least one assist signal having an assist enable logic level in response to the first power supply potential having a first potential and generates the at least one assist signal having an assist disable logic level in response to the first power supply potential having a second potential when the semiconductor device is in the normal mode of operation and the first circuit generates the at least one assist signal having the assist enable logic level in the test mode of operation when the first power supply potential is at the first potential and when the first power supply potential is at the second potential, wherein

the at least one assist signal alters at least one feature of a read operation or a write operation to a static random access memory (SRAM) cell when the at least one assist signal has the assist enable logic level.

11. The semiconductor device of claim 10, further including:

the at least one assist signal includes a read assist signal.

12. The semiconductor device of claim 11, further including:

a word line voltage circuit coupled to receive the read assist signal, the word line voltage circuit provides a word line potential that is substantially less than the first power supply potential in response to the read assist signal having the assist enable logic level and provides a word line potential that is essentially the same potential as the first power supply potential when the read assist signal has the assist disable logic level wherein the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the read operation, wherein

the at least one feature includes the word line potential during the read operation.

13. The semiconductor device of claim 11, further including:

a sense amplifier circuit coupled to receive data from the SRAM cell during a read operation and provide a data output signal, the sense amplifier circuit includes a threshold voltage compensation circuit that provides compensation for differences in threshold voltages in a first insulated gate field effect transistor (IGFET) and a second IGFET of the sense amplifier circuit during the read operation of data from the SRAM cell, wherein

the read assist signal enables the threshold voltage compensation circuit when the read assist signal has the assist enable logic level and disables the threshold voltage compensation circuit when the read assist signal has the assist disable logic level, and the least one feature includes enabling the threshold voltage compensation circuit during the read operation.

14. The semiconductor device of claim 10, wherein:

the at least one assist signal includes a write assist signal.

15. The semiconductor device of claim 12, further including:

a write voltage selection circuit coupled to receive the write assist signal and provide a write potential; and

a write driver circuit coupled to receive the write potential and drive a first bit line connected to the SRAM cell essentially to the write potential during a write operation, wherein

the first power supply potential provides an upper power rail to the semiconductor device and a reference potential provides a lower power rail to the semiconductor device and the write voltage selection circuit provides a write potential that is substantially less than the reference potential when the write assist signal has the assist enable logic level and provides a write potential that is essentially the reference potential when the write assist signal has the assist disable logic level, and the at least one feature includes providing the write potential during the write operation.

16. The semiconductor device of claim 14, further including:

a word line voltage circuit coupled to receive the write assist signal and provide a word line potential, wherein

the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the write operation and the word line voltage circuit provides a word line potential that is substantially greater than the first power supply potential when the write assist signal has the assist enable logic level and provides a word line potential that is essentially the first power supply potential when the write assist signal has the assist disable logic level, and the at least one feature includes the word line potential during the write operation.

17. The semiconductor device of claim 12, further including:

an array cell voltage circuit coupled to receive the write assist signal and provide a cell power supply potential, wherein

the SRAM cell is coupled to receive and is powered by the cell power supply potential and the array cell voltage circuit provides a cell power supply potential that is substantially less than the first power supply potential when the write assist signal has the assist enable logic level and provides a cell power supply potential that is essentially the first power supply potential when the write assist signal has the assist disable logic level, and the at least one feature includes the cell power supply potential during the write operation.

18. The semiconductor device of claim 10, further including:

the semiconductor device has a temperature and the first circuit generates the at least one assist signal in response to the potential of the first power supply potential and the temperature of the semiconductor device when the semiconductor device is in the normal mode of operation.

19. The semiconductor device of claim 10, wherein:

the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.

20. The semiconductor device of claim 19, wherein:

the processor circuit portion and the SRAM circuit portion are connected by a bus for carrying data between the processor circuit portion and the SRAM circuit portion.