Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
First Claim
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1. A semiconductor device that has a normal mode of operation and a test mode of operation, comprising:
- a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level;
the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation.
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Abstract
A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation.
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Citations
20 Claims
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1. A semiconductor device that has a normal mode of operation and a test mode of operation, comprising:
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a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device powered by a first power supply potential, comprising:
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the semiconductor device has a normal mode of operation and a test mode of operation; and a first circuit that generates at least one assist signal having an assist enable logic level in response to the first power supply potential having a first potential and generates the at least one assist signal having an assist disable logic level in response to the first power supply potential having a second potential when the semiconductor device is in the normal mode of operation and the first circuit generates the at least one assist signal having the assist enable logic level in the test mode of operation when the first power supply potential is at the first potential and when the first power supply potential is at the second potential, wherein the at least one assist signal alters at least one feature of a read operation or a write operation to a static random access memory (SRAM) cell when the at least one assist signal has the assist enable logic level. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification