Alignment marks in substrate having through-substrate via (TSV)

• US 10,163,706 B2
• Filed: 12/30/2014
• Issued: 12/25/2018
• Est. Priority Date: 09/02/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hsin, Tsai, Fang Wen, Lin, Jing-Cheng, Chiou, Wen-Chih, Jeng, Shin-Puu
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US14/586,276
• Publication Number:
  US 20150118840A1
• Time in Patent Office: 1,456 Days
• Field of Search: None
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Claims

1. A method comprising:

performing a backside grinding on a substrate to expose an alignment through-substrate via (TSV) and a function TSV, wherein a back surface of the substrate is exposed after the backside grinding, the alignment TSV formed from three or more straight conductive segments in a plan view;

forming a passivation layer contacting the back surface, wherein the passivation layer is formed as a blanket layer, and wherein the alignment and the functional TSVs penetrate through the passivation layer; and

forming a conductive feature on a backside of the substrate, wherein the conductive feature is electrically coupled to the functional TSV, and the forming the conductive feature is performed using the alignment TSV as an alignment mark, wherein the alignment TSV and the functional TSV are a same width.

2. The method of claim 1 further comprising forming the alignment and the functional TSVs comprising:

etching the back surface of the substrate, with ends of the alignment and the functional TSVs protruding beyond the back surface of the substrate, wherein a space is left by an etched back surface layer of the substrate, and the passivation layer is filled into the space; and

removing portions of the passivation layer that overlap the alignment and the functional TSVs to expose the alignment and the functional TSVs.

3. The method of claim 1, wherein the forming the conductive feature comprises forming a redistribution line.

4. The method of claim 1, wherein when the conductive feature is formed, no conductive feature is formed to electrically couple to the alignment TSV.

5. The method of claim 1 further comprising forming an additional alignment mark on a front side of, and outside of, the substrate, wherein a position of the alignment TSV is aligned relative to the additional alignment mark, wherein the additional alignment mark is different from the alignment TSV.

6. The method of claim 1 further comprising forming an interconnect structure on a front side of the substrate, wherein no conductive feature in the interconnect structure is electrically coupled to the alignment TSV.

7. The method of claim 1, wherein the substrate comprises:

a front surface opposite to the back surface of the substrate, with the back surface on the backside; and

a transistor is formed at the front surface of the substrate.

8. The method of claim 1, wherein when the alignment TSV is used as the alignment mark, the back surface of the substrate is covered by the passivation layer.

9. A method comprising:

forming a first conductive through-substrate via (TSV) and a second conductive TSV in a substrate, the substrate having a front side and a backside, the first conductive TSV having a first width in a direction parallel to the backside, the second TSV having a second width in the direction parallel to the backside, the second width equal to the first width;

forming an interconnect structure on the front side of the substrate, wherein the second TSV in the substrate is electrically coupled to metal lines and vias in the interconnect structure, and no metal line and via in the interconnect structure is electrically coupled to the first conductive TSV in the substrate;

performing a backside grinding on the substrate to expose the first conductive TSV and the second conductive TSV, wherein the backside grinding is performed from the backside of the substrate;

forming a passivation layer over a back surface of the substrate, the first conductive TSV and the second conductive TSV penetrating through the passivation layer;

forming an under-bump metallurgy (UBM) layer on the passivation layer, the UBM layer being over the back surface of the substrate, the first conductive TSV, and the second conductive TSV;

forming a conductive feature on the UBM layer, wherein the conductive feature is electrically coupled to the second conductive TSV, and wherein when the conductive feature is formed, a position of the conductive feature is determined using the first conductive TSV that penetrates through the passivation layer as an alignment mark, and wherein no conductive feature is formed to connect to the first conductive TSV; and

removing portions of the UBM layer over the first conductive TSV and the back surface of the substrate.

10. The method of claim 9, wherein the forming the conductive feature comprises forming a redistribution line.

11. The method of claim 9, wherein the forming the conductive feature comprises forming a metal bump.

12. The method of claim 9, wherein the substrate comprises a front surface and the back surface opposite to the front surface, with the back surface being on the backside of the substrate, wherein a transistor is formed at the front surface of the substrate.

13. The method of claim 9 further comprising:

etching the back surface of the substrate, with ends of the first and the second conductive TSVs protruding beyond the back surface of the substrate, wherein a space is left by an etched back surface layer of the substrate;

forming the passivation layer on the back surface of the substrate, wherein the passivation layer is filled into the space; and

removing portions of the passivation layer that overlap the first and the second conductive TSVs to expose the first and the second conductive TSVs.

14. A method comprising:

simultaneously forming a group of alignment through-substrate vias (TSVs) and a group of functional TSVs in a substrate, the group of alignment TSVs arranged in a rectangular region substantially free of each of the group of functional TSVs, each of the group of functional TSVs electrically coupling first conductive features on a back surface of the substrate to second conductive features on a front surface of the substrate;

performing a backside grinding from a backside of the substrate, wherein the group of alignment TSVs and the group of functional TSVs are exposed through the back surface of the substrate;

after the backside grinding, recessing the back surface of the substrate to allow the group of alignment TSVs and the group of functional TSVs to protrude beyond the back surface, wherein a space is left by an etched back surface layer of the substrate removed in the recessing;

forming a passivation layer on the back surface of the substrate, wherein the passivation layer is filled into the space;

removing portions of the passivation layer that overlap the group of alignment TSVs to expose the group of alignment TSVs; and

with the passivation layer covering the back surface of the substrate, forming the first conductive features on the back surface of the substrate and electrically coupled to at least one TSV of the group of functional TSVs, with the group of alignment TSVs used as an alignment mark for positioning the first conductive features.

15. The method of claim 14, wherein the first conductive features comprise at least one of a redistribution line and a metal bump.

16. The method of claim 14, wherein no additional conductive feature is formed simultaneously as the first conductive features to electrically couple to the group of alignment TSVs.

17. The method of claim 14 further comprising forming an interconnect structure on a front side of the substrate, wherein no conductive feature in the interconnect structure is electrically coupled to the group of alignment TSVs.

18. The method of claim 14, wherein the substrate further comprises the front surface opposite to the back surface, wherein a transistor is formed at the front surface of the substrate.

19. The method of claim 14, wherein when the group of alignment TSVs is used as the alignment mark, wherein the group of alignment TSVs is exposed through openings in the passivation layer.