Method and structure for FinFet isolation

• US 10,163,722 B2
• Filed: 11/13/2017
• Issued: 12/25/2018
• Est. Priority Date: 10/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Lin, Jr-Jung
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US15/810,616
• Publication Number:
  US 20180068900A1
• Time in Patent Office: 407 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a substrate; first and second fins over the substrate and extending lengthwise generally along a first direction; first and second gate stacks over the substrate and the first and second fins respectively; and a first isolation structure disposed between the first and second fins and extending lengthwise generally along a second direction perpendicular to the first direction, wherein the first isolation structure is adjacent to a first source/drain (S/D) region in the first fin and adjacent to a second S/D region in the second fin.

Claims

1. A semiconductor device, comprising:

a substrate;

first and second fins over the substrate and extending lengthwise generally along a first direction;

a first gate stack over the substrate and the first fin;

a second gate stack over the substrate and the second fin; and

a first isolation structure disposed between the first and second fins and extending lengthwise generally along a second direction perpendicular to the first direction, wherein the first isolation structure is adjacent to a first source/drain (S/D) region in the first fin and adjacent to a second S/D region in the second fin.

2. The semiconductor device of claim 1, further comprising one or more dielectric layers over the first fin and laterally between the first gate stack and the first isolation structure.

3. The semiconductor device of claim 1, further comprising:

spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the first isolation structure.

4. The semiconductor device of claim 3, wherein the spacer features completely surround the first isolation structure from a top view.

5. The semiconductor device of claim 1, wherein a bottom surface of the first isolation structure is below a bottom surface of the first gate stack.

6. The semiconductor device of claim 1, wherein the first isolation structure includes a first portion above the first and second fins and a second portion between the first and second fins, and the first portion is narrower than the second portion along the first direction.

7. The semiconductor device of claim 6, wherein the first portion includes a portion of a first dielectric layer and the second portion includes another portion of the first dielectric layer and a second dielectric layer surrounding sidewalls and bottom surfaces of the another portion of the first dielectric layer.

8. The semiconductor device of claim 1, further comprising:

a second isolation structure disposed over an end of the first fin and extending lengthwise generally along the second direction, wherein the first gate stack is disposed between the first and second isolation structures.

9. A semiconductor device, comprising:

a substrate;

first and second fins over the substrate and extending lengthwise generally along a same direction;

a first isolation structure over the substrate, wherein the first and second fins protrude above a top surface of the first isolation structure;

first and second gate stacks over the top surface of the first isolation structure and engaging the first and second fins respectively;

a second isolation structure disposed between the first and second fins and in physical contact with the first and second fins; and

spacer features on sidewalls of an upper portion of the second isolation structure.

10. The semiconductor device of claim 9, further comprising:

one or more dielectric layers over the first fin and laterally between the first gate stack and the second isolation structure.

11. The semiconductor device of claim 9, further comprising:

a third isolation structure disposed over and in physical contact with an end of the first fin, wherein the first gate stack is disposed between the second and the third isolation structures.

12. The semiconductor device of claim 9, wherein the upper portion of the second isolation structure is narrower than a lower portion of the second isolation structure that is disposed below a top surface of the first fin.

13. The semiconductor device of claim 12, wherein the lower portion of the second isolation structure includes a first dielectric layer disposed over a second dielectric layer.

14. The semiconductor device of claim 9, wherein a bottom surface of the second isolation structure is below a top surface of the first isolation structure.

15. A semiconductor device, comprising:

a substrate;

first and second fins over the substrate and extending lengthwise generally along a same direction;

a first gate stack over the substrate and engaging the first fin;

a second gate stack over the substrate and engaging the second fin;

a first isolation structure over and physically contacting a first end of the first fin;

a second isolation structure over and physically contacting a first end of the second fin; and

a third isolation structure between the first and second fins and in physical contact with a second end of the first fin and a second end of the second fin.

16. The semiconductor device of claim 15, wherein a bottom surface of the third isolation structure is lower than a bottom surface of the first and second gate stacks.

17. The semiconductor device of claim 15, wherein the first and the third isolation structure comprises a same material.

18. The semiconductor device of claim 15, wherein the first and the third isolation structure comprises different materials.

19. The semiconductor device of claim 15, further comprising spacer features on sidewalls of the first and second gate stacks, on sidewalls of the first and second isolation structures, and on sidewalls of an upper portion of the third isolation structure.

20. The semiconductor device of claim 15, further comprising one or more dielectric layers over the first and second fins and laterally filling space among the first, second, and third isolation structures and the first and second gate stacks.