Isolation structure for stacked dies

• US 10,163,756 B2
• Filed: 04/16/2014
• Issued: 12/25/2018
• Est. Priority Date: 01/05/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Hsu, Kuo-Ching, Chen, Chen-Shien, Chiou, Wen-Chih, Yu, Chen-Hua
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): Jones, Eric W
• Application Number:
  US14/254,597
• Publication Number:
  US 20140225277A1
• Time in Patent Office: 1,714 Days
• Field of Search: 257684-734, 438458, 438597, 438107
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed.

Claims

1. A device comprising:

a substrate having an opening formed therein, the opening having sidewalls extending from a circuit side of the substrate to a backside of the substrate;

a through via formed of conductive material disposed in the opening, wherein the through via has a first side and second, opposing side, the second side extending beyond the backside of the substrate, wherein the through via has sidewalls extending between the first and second side, wherein the sidewalls are substantially straight between the first side and second side;

a liner layer disposed on at least a portion of the sidewalls of the opening adjacent the through via;

an isolation film disposed over the backside of the substrate, wherein a topmost surface of the liner layer and a topmost surface of the isolation film are level with the second side of the through via;

a conductive cap layer over the second side of the through via, the conductive cap layer having a substantially flat upper surface, the conductive cap layer being a non-conformal layer; and

a solder material directly disposed on at least a portion of the flat upper surface of the conductive cap layer.

2. The device of claim 1, further comprising:

one or more intermetal dielectric (IMD) layers disposed on the circuit side of the substrate;

metal contacts disposed over the circuit side of the substrate in an uppermost one of the one or more IMD layers; and

conductive bumps disposed on the metal contacts.

3. The device of claim 1, further comprising:

an active device formed on the circuit side of the substrate; and

a metallization layer disposed on the circuit side of the substrate and connecting a first end of the through via at the circuit side of the substrate to the active device.

4. The device of claim 1 further comprising:

an etch stop layer on the circuit side of the substrate, wherein the through via extends through the etch stop layer; and

electrical circuitry extending from the circuit side of the substrate.

5. The device of claim 1, wherein the isolation film and the liner layer are the same material.

6. The device of claim 1, wherein a bottommost surface of the solder material is separated from a surface of the isolation film and a surface of the liner layer.

7. A semiconductor device, comprising:

a substrate having a first side and a second side opposite the first side and an opening extending through the substrate from the first side to the second side;

a liner layer disposed directly on a surface of the opening;

a conductive through via formed on the liner layer and filling the opening, the conductive through via having at least a portion of the through via protruding from the second side of the substrate;

a dielectric layer over the second side of the substrate, the dielectric layer having a first surface in contact with the substrate and having a second surface opposite the first surface, wherein the dielectric layer and the liner layer are the same material;

a conductive pad disposed on the second side of the substrate and on the conductive through via, the conductive pad having substantially straight sidewalls that are substantially perpendicular to a surface of the second side of the substrate, wherein at least a portion of the dielectric layer is disposed between the conductive through via and the conductive pad along a line parallel to the surface of the second side of the substrate, wherein the conductive pad is a non-conformal layer, wherein the conductive pad comprises copper;

circuitry on the first side of the substrate; and

an etch stop layer disposed on the first side of the substrate, the etch stop layer adjacent to the circuitry.

8. The semiconductor device of claim 7, wherein the conductive pad has a substantially flat top surface.

9. The semiconductor device of Claim 8, wherein the conductive pad comprises copper throughout.

10. The semiconductor device of claim 7, wherein the second surface of the dielectric layer is non-planar.

11. The semiconductor device of claim 7, wherein at least a portion of the liner layer is disposed between the conductive through via and the dielectric layer.

12. The semiconductor device of claim 7, further comprising a seed layer interposed between the conductive pad and the through via.

13. The semiconductor device of claim 7, further comprising a flowable material disposed directly on the conductive pad.

14. A semiconductor device, comprising:

a substrate having an opening extending from a circuit side through the substrate to a backside of the substrate;

a passivation layer having a first surface on the backside of the substrate and having a second surface opposite the first surface;

a liner layer directly on a surface of the opening, wherein the passivation layer and the liner layer are the same material;

a through via on the liner layer and filling the opening, a portion of the through via exposed through the liner layer;

a conductive pillar disposed on the backside of the substrate and on the through via, the conductive pillar being a non-conformal layer having substantially straight sidewalls that are substantially perpendicular to a surface of the backside of the substrate, wherein at least a portion of the passivation layer is disposed between the through via and the conductive pillar along a line parallel to the surface of the backside of the substrate, wherein the conductive pillar continuously contacts the passivation layer from outermost extents of the conductive pillar to the through via, wherein the conductive pillar comprises copper;

one or more intermetal dielectric (IMD) layers disposed on the circuit side of the substrate;

metal contacts disposed over the circuit side in an uppermost IMD layer of the one or more IMD layers; and

conductive bumps disposed over the uppermost IMD layer and on the metal contacts.

15. The semiconductor device of claim 14, wherein at least one of the IMD layers covers a first end of the through via, and wherein a metallization layer disposed in the one or more IMD layers connects the first end of the through via to an active device formed on the circuit side of the substrate.

16. The semiconductor device of claim 15, wherein a lowermost surface of the through via is disposed between the metallization layer and the substrate.

17. The semiconductor device of claim 14 further comprising an etch stop layer on the circuit side of the substrate, wherein the through via extends through the etch stop layer.

18. The semiconductor device of claim 14, wherein an upper surface of the passivation layer is non-planar.

19. The semiconductor device of claim 14, wherein the conductive pillar comprises a conductive pad over a seed layer.

20. The semiconductor device of claim 14, wherein the conductive pillar has a substantially flat top surface.

21. The semiconductor device of Claim 14, further comprising a flowable material directly on the conductive pillar.