Protrusion bump pads for bond-on-trace processing

• US 10,163,774 B2
• Filed: 01/21/2016
• Issued: 12/25/2018
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Yu-Min, Wu, Jiun Yi
• Primary Examiner(s): Zarneke, David A
• Application Number:
  US15/003,632
• Publication Number:
  US 20160155697A1
• Time in Patent Office: 1,069 Days
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11614 by chemical means only
• CPC Class Codes: H01L 2224/11622 Photolithography
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13294 with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
• CPC Class Codes: H01L 2224/133 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/1712 Layout layout of bump connectors prior to the connecting process H01L2224/1412
• CPC Class Codes: H01L 2224/17132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/81424 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81444 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81466 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/0533 : 3rd Group
• CPC Class Codes: H01L 2924/0534 : 4th Group
• CPC Class Codes: H01L 2924/05342 : ZrO2
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/05994 : having an amorphous microstructure, i.e. glass
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1531 : the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/20641 : larger or equal to 100 microns less than 200 microns
• CPC Class Codes: H05K 1/0268 : for electrical inspection or testing
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/0989 : Coating free areas, e.g. areas other than pads or lands free of solder resist
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/0353 : Making conductive layer thin, e.g. by etching selective thinning for providing different thickness H05K2203/0369
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

Claims

1. An apparatus, comprising:

a substrate;

conductive traces at a first side of the substrate;

conductive members extending into the substrate from corresponding conductive traces; and

bump pads protruding from a first subset of the conductive traces;

an integrated circuit chip over the substrate; and

conductive bumps coupled between the integrated circuit chip and the bump pads, wherein the conductive bumps cover upper surfaces of the bump pads and cover at least upper sidewalls of the bump pads, wherein lower surfaces of the bump pads are level with an upper surface of a topmost dielectric layer of the substrate, wherein the lower surfaces of the bump pads physically contact respective upper surfaces of the first subset of the conductive traces, wherein the bump pads and the first subset of the conductive traces have a same width, wherein the upper surfaces of the first subset of the conductive traces are level with the upper surface of the topmost dielectric layer, wherein upper surfaces of a second subset of the conductive traces are recessed from the upper surface of the top dielectric layer of the substrate, wherein lower surfaces of the second subset of the conductive traces and lower surfaces of the first subset of the conductive traces are level with a lower surface of the topmost dielectric layer.

2. The apparatus of claim 1, wherein the conductive members are conductive pillars extending to corresponding conductive features disposed on a second side of the substrate opposing the first side.

3. The apparatus of claim 1, wherein the conductive traces are laterally offset from one another by a minimum trace pitch, the bump pads are laterally offset from one another by a minimum bump pad pitch, and the minimum bump pad pitch is substantially greater than the minimum trace pitch.

4. The apparatus of claim 1, wherein the conductive traces are laterally offset from one another by a minimum trace pitch, the bump pads are laterally offset from one another by a minimum bump pad pitch, and the minimum bump pad pitch is at least about twice the minimum trace pitch.

5. The apparatus of claim 1, wherein the conductive bumps are laterally offset from one another by a minimum bump pitch of less than about no microns.

6. The apparatus of claim 1, wherein the substrate comprises a stack of insulating layers having respective embedded conductive elements embedded therein.

19. The apparatus of claim 1, wherein each of the first subset of the conductive traces is laterally spaced from an adjacent conductive trace of the second subset of the conductive traces by a first distance, wherein the first distance is between about 300 microns and about 500 microns.

20. The apparatus of claim 1, wherein the conductive bumps comprise solder.

7. An apparatus comprising:

a build-up layer having a first topmost surface and a first bottommost surface, the first topmost surface being an upper surface of a topmost dielectric layer of the build-up layer;

a first conductive trace in the topmost dielectric layer, an upper surface of the first conductive trace being level with the first topmost surface, a lower surface of the first conductive trace being level with a lower surface of the topmost dielectric layer, the first conductive trace having a first uniform width;

a first bump pad contacting and protruding from the first conductive trace, the first bump pad extending above the first topmost surface, the first bump pad having a second uniform width that is the same as the first uniform width;

a second conductive trace in the topmost dielectric layer, the second conductive trace having a second topmost surface and a second bottommost surface, wherein the second topmost surface is recessed from the first topmost surface of the build-up layer and is closer to the first topmost surface of the build-up layer than the second bottommost surface, wherein the second bottommost surface is level with the lower surface of the topmost dielectric layer; and

a conductive pillar extending from the first conductive trace to the first bottommost surface of the build-up layer.

8. The apparatus of claim 7, further comprising:

a third conductive trace formed at the first topmost surface;

a second bump pad protruding from the third conductive trace and extending above the first topmost surface; and

wherein the second conductive trace extends parallel to the first topmost surface of the build-up layer and extends between the first bump pad and the second bump pad.

9. The apparatus of claim 8, wherein the first bump pad and the second bump pad are laterally offset from one another by a pitch of less than about no microns.

10. The apparatus of claim 8, further comprising:

an integrated circuit die having a first contact pad bonded to the first bump pad and having a second contact pad bonded to the second bump pad.

11. The apparatus of claim 10, further comprising a first solder bump bonding the first contact pad to the first bump pad and a second solder bump bonding the second contact pad to the second bump pad.

12. The apparatus of claim 7, wherein the build-up layer comprises multiple dielectric layers and metallization formed within the dielectric layers.

13. The apparatus of claim 12, wherein the dielectric layers comprise a material selected from the group consisting of prepreg, ajinomoto build-up film, paper, glass fiber, and non-woven glass fabric.

14. The apparatus of claim 12, wherein the dielectric layers comprise a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, an oxide, a nitrogen containing oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, and combinations thereof.

15. An apparatus comprising:

conductive traces disposed in a topmost dielectric layer of a build-up layer; and

bump pads, respective bump pads protruding from respective ones of a first subset of the conductive traces, wherein the first subset of the conductive traces have a bottommost surface that is level with a lower surface of the topmost dielectric layer and a topmost surface that is level with an upper surface of the topmost dielectric layer, wherein a second subset of the conductive traces have a bottommost surface that is level with the bottommost surface of the first subset of the conductive traces and a topmost surface that is recessed within the topmost dielectric layer of the build-up layer, wherein the bump pads and the first subset of the conductive traces have a same width such that sidewalls of the bump pads and respective sidewalls of the first subset of the conductive traces are aligned.

16. The apparatus of claim 15, further comprising a plurality of conductive pillars extending from at least one of the conductive traces through the build-up layer from a first side of the build-up layer to a second side of the build-up layer opposing the first side.

17. The apparatus of claim 15, wherein the conductive traces are laterally offset from one another by a minimum trace pitch, the bump pads are laterally offset from one another by a minimum bump pad pitch, and the minimum bump pad pitch is greater than the minimum trace pitch.

18. The apparatus of claim 15, wherein the conductive traces are laterally offset from one another by a minimum trace pitch, the bump pads are laterally offset from one another by a minimum bump pad pitch, and the minimum bump pad pitch is at least twice the minimum trace pitch.