Semiconductor structure

• US 10,163,787 B2
• Filed: 06/30/2017
• Issued: 12/25/2018
• Est. Priority Date: 10/12/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Hui Yu, Kuo, Feng Wei, Kuan, Jui-Feng, Cheng, Yi-Kan
• Primary Examiner(s): Nicely, Joseph C
• Assistant Examiner(s): Vuong, Thai T
• Application Number:
  US15/639,379
• Publication Number:
  US 20170300611A1
• Time in Patent Office: 543 Days
• Field of Search: 257773
• CPC Class Codes: G03F 1/38 Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 1/88 prepared by photographic processes for production of originals simulating relief
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2223/6638 Differential pair signal lines
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.

Claims

1. A semiconductor structure comprising:

a first conductive path extending in a first direction, wherein the first conductive path comprises a first segment and a second segment, the first segment is in a first conductive layer, the second segment is in a second conductive layer different from the first conductive layer, and the first segment is electrically connected to the second segment;

a second conductive path extending in the first direction, wherein the second conductive path comprises a third segment and a fourth segment, the third segment is in the first conductive layer, the fourth segment is in the second conductive layer, and the third segment is electrically connected to the fourth segment; and

a third conductive path extending in the first direction, wherein the third conductive path is between the first conductive path and the second conductive path in a second direction perpendicular to the first direction, the third conductive path comprises a fifth segment and a sixth segment, the fifth segment is in the second conductive layer, the sixth segment is in the first conductive layer, and the fifth segment is electrically connected to the sixth segment,

wherein an area of the first conductive layer between the first segment and the third segment is free of the sixth segment.

2. The semiconductor structure of claim 1, wherein a length of the first segment is equal to a length of the second segment.

3. The semiconductor structure of claim 1, wherein a length of the first segment is different from a length of the second segment.

4. The semiconductor structure of claim 1, wherein a length of the first segment is equal to a length of the fourth segment.

5. The semiconductor structure of claim 1, wherein a length of the first segment is different from a length of the fourth segment.

6. The semiconductor structure of claim 1, wherein the first conductive path further comprises an additional segment, the additional segment is on the first conductive layer, and the second segment is electrically between the first segment and the additional segment.

7. The semiconductor structure of claim 1, further comprising a fourth conductive path extending in the first direction, wherein the second conductive path is between the third conductive path and the fourth conductive path in the second direction, the fourth conductive path comprises a seventh segment and an eighth segment, the seventh segment is in the second conductive layer, the eighth segment is in the first conductive layer, and the seventh segment is electrically connected to the eighth segment.

8. A semiconductor structure comprising:

a first pair of differential signal lines extending in a first direction, wherein each differential signal line of the first pair of differential lines comprises a first segment and a second segment, the first segment is in a first conductive layer, the second segment is in a second conductive layer different from the first conductive layer, and the first segment is electrically connected to the second segment for each corresponding differential signal line of the first pair of differential signal lines; and

a second pair of differential signal lines extending in the first direction, wherein at least one differential signal line of the second pair of differential signal lines is between adjacent differential signal lines of the first pair of differential signal lines in a second direction perpendicular to the first direction, each differential signal line of the second pair of differential lines comprises a third segment and a fourth segment, the third segment is in the second conductive layer, the fourth segment is in the first conductive layer, and the third segment is electrically connected to the fourth segment for each corresponding differential signal line of the second pair of differential signal lines,

wherein an area of the first conductive layer between first segments of the first pair of differential signal lines is free of the fourth segment of each differential signal line of the second pair of differential signal lines.

9. The semiconductor structure of claim 8, wherein each segment of each differential signal line of the first pair of differential signal lines has a same length.

10. The semiconductor structure of claim 9, wherein each segment of each differential signal line of the second pair of differential signal lines has a same length.

11. The semiconductor structure of claim 8, wherein at least one segment of a first differential signal line of the first pair of differential signal lines has a different length from another segment of a second differential signal line of the first pair of differential signal lines.

12. The semiconductor structure of claim 11, wherein at least one segment of a first differential signal line of the second pair of differential signal lines has a different length from another segment of a second differential signal line of the second pair of differential signal lines.

13. The semiconductor structure of claim 8, wherein a first differential signal line of the first pair of differential signal lines is between adjacent differential signal lines of the second pair of differential signal lines.

14. The semiconductor structure of claim 8, wherein the first conductive layer is farther from a substrate than the second conductive layer.

15. The semiconductor structure of claim 8, wherein the first conductive layer is closer to a substrate than the second conductive layer.

16. A semiconductor structure comprising:

a first conductive path extending in a first direction, wherein the first conductive path comprises a first segment and a second segment, the first segment is in a first conductive layer, the second segment is in a second conductive layer different from the first conductive layer, and the first segment is electrically connected to the second segment;

a second conductive path extending in the first direction, wherein the second conductive path comprises a third segment and a fourth segment, the third segment is in the first conductive layer, the fourth segment is in the second conductive layer, and the third segment is electrically connected to the fourth segment; and

a third conductive path extending in the first direction, wherein the third conductive path is between the first conductive path and the second conductive path in a second direction perpendicular to the first direction, the third conductive path comprises a fifth segment and a sixth segment, the fifth segment is in the second conductive layer, the sixth segment is in the first conductive layer, and the fifth segment is electrically connected to the sixth segment,

wherein a first area of the first conductive layer extending in the second direction is free of the first segment, and the first area of the first conductive layer contains the third segment and the sixth segment.

17. The semiconductor structure of claim 16, wherein a second area of the first conductive layer extending in the second direction is free of at least one of the third segment or the sixth segment, and the second area of the first conductive layer contains the first segment.

18. The semiconductor structure of claim 16, further comprising a fourth conductive path extending in the first direction, wherein the second conductive path is between the third conductive path and the fourth conductive path in the second direction, the fourth conductive path comprises a seventh segment and an eighth segment, the seventh segment is in the second conductive layer, the eighth segment is in the first conductive layer, and the seventh segment is electrically connected to the eighth segment.

19. The semiconductor structure of claim 18, wherein the first area of the first conductive layer is free of the eighth segment.

20. The semiconductor structure of claim 18, wherein a second area of the first conductive layer extending in the second direction is free of at least one of the third segment or the sixth segment, and the second area of the first conductive layer contains the first segment and the eighth segment.