Shielding for through-silicon-via noise coupling

• US 10,163,809 B2
• Filed: 11/18/2015
• Issued: 12/25/2018
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Horng, Jaw-Juinn, Hsieh, Chung-Peng
• Primary Examiner(s): Kim, Su C
• Application Number:
  US14/944,907
• Publication Number:
  US 20160071806A1
• Time in Patent Office: 1,133 Days
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.

Claims

1. An integrated circuit device, comprising:

a semiconductor substrate;

an active area disposed in the semiconductor substrate;

a first guard ring disposed in the semiconductor substrate and entirely surrounding the active area, the first guard ring having a first conductivity type;

a via penetrating through the semiconductor substrate and being spaced apart from the active area such that the via is disposed outside of the first guard ring; and

a second guard ring disposed in the semiconductor substrate, the second guard ring including a first ringlet and a second ringlet which adjoin one another at a common side to establish a first area and a second area, which are separated from one another by the common side, the first ringlet and the common side collectively surrounding and spaced apart from the via by a portion of the semiconductor substrate and not in direct contact with the via, and the second ringlet and the common side collectively surrounding and spaced apart from the first guard ring.

2. The integrated circuit device of claim 1, wherein a linear axis passes through the active area and the via, and the common side is located in a region of the linear axis between the active area and the via.

3. The integrated circuit device of claim 2, wherein the first ringlet has a first ring thickness on at least one side of the first ringlet other than the common side, and the common side has a second thickness in the region, the second thickness being greater than the first ring thickness.

4. The integrated circuit device of claim 1, wherein:

the via and the active area are no more than 35 μ

m apart.

5. The integrated circuit device of claim 1, wherein the active area is at least 100 μ

m².

6. The integrated circuit device of claim 1, wherein the first and second guard rings are electrically coupled to ground pads.

7. The integrated circuit device of claim 1, wherein the first and second guard rings are electrically coupled to the same ground pad.

8. The integrated circuit device of claim 1, wherein the first and second guard rings are electrically coupled to distinct ground pads.

9. The integrated circuit device of claim 1, wherein the active area is formed within an n-well.

10. A 3D integrated circuit device, comprising:

first and second semiconductor substrates;

an active area disposed in the first semiconductor substrate;

a first guard ring disposed in the first semiconductor substrate and entirely surrounding the active area;

a via penetrating through the first semiconductor substrate and being spaced apart from the active area such that the via is disposed outside of the first guard ring, the via forming a connection with a circuit disposed in or on the second substrate; and

a second guard ring disposed in the first semiconductor substrate, the second guard ring including a first ringlet and a second ringlet which adjoin one another at a common side to establish the second guard ring, the first ringlet and the common side collectively surrounding the via and being spaced apart from the via and not in direct contact with the via, and the second ringlet and the common side collectively surrounding the first guard ring.

11. The 3D integrated circuit device of claim 10 wherein:

the first ringlet has a first ring thickness on at least one side of the first ringlet other than the common side, and wherein the common side has a second thickness, the second thickness being greater than the first ring thickness.

12. The 3D integrated circuit of claim 10, wherein:

the first guard ring operates as a first ground having a first noise characteristic; and

the second guard ring operates as a second ground having a second noise characteristic, wherein the first noise characteristic is different from the second noise characteristic.

13. The 3D integrated circuit device of claim 10, wherein the first and second guard rings have a first doping type, which is p-type, and the first and second guard rings are p-doped to at least a first concentration.

14. The 3D integrated circuit device of claim 10, wherein the first guard ring is doped to a first concentration and the first semiconductor substrate is doped to a second concentration that is less than the first concentration.

15. An integrated circuit device, comprising:

a semiconductor substrate;

a through substrate via extending through the semiconductor substrate;

a first guard ring disposed in the semiconductor substrate and having a first conductivity type, the first guard ring including a first ringlet and a second ringlet which adjoin one another at a common side to establish the first guard ring, the first ringlet surrounding the through substrate via and spaced apart from the through substrate via by a portion of the semiconductor substrate having a second conductivity type opposite the first conductivity type such that the first ringlet is not in direct contact with the via;

an active area disposed within the semiconductor substrate and being surrounded by the second ringlet such that the common side separates the active area from the through substrate via; and

a second guard ring surrounding the active area and having the first conductivity type, the second guard ring being disjoint from the first guard ring and being entirely surrounded by the second ringlet of the first guard ring.

16. The integrated circuit device of claim 15 wherein:

the first ringlet has a first ring thickness on at least one side of the first ringlet other than the common side, and wherein the common side has a second thickness, the second thickness being greater than the first ring thickness.

17. The integrated circuit device of claim 15, wherein:

the first guard ring operates as a first ground having a first noise characteristic; and

the second guard ring operates as a second ground having a second noise characteristic, wherein the first noise characteristic is different from the second noise characteristic.

18. The integrated circuit device of claim 15, wherein the first conductivity type is p-type and the first and second guard rings are p-doped to at least a first concentration.

19. The integrated circuit device of claim 15, wherein the first guard ring is doped to a first concentration and the semiconductor substrate is doped to a second concentration that is different than the first concentration.

20. The integrated circuit device of claim 19, wherein the second concentration is less than the first concentration.