Multichip modules and methods of fabrication

• US 10,163,833 B2
• Filed: 05/02/2017
• Issued: 12/25/2018
• Est. Priority Date: 09/05/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Invensas Corporation
• Inventors: Wang, Liang, Katkar, Rajesh, Shen, Hong
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US15/584,961
• Publication Number:
  US 20170236794A1
• Time in Patent Office: 602 Days
• Field of Search: 257686
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/33517 including layer connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48135 Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/92124 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92133 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/10 : the devices having separate containers
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/1511 : Structure
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips'"'"' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

Claims

1. An assembly comprising:

a wiring board comprising a plurality of contact pads at each of a top side and a bottom side of the wiring board;

a first multi-chip module directly connected to the plurality of contact pads on the top side of the wiring board;

a second multi-chip module directly connected to the plurality of contact pads on the bottom side of the wiring board;

each of the first multi-chip module and the second multi-chip module comprising;

a plurality of first chips, each first chip of the plurality of first chips comprising;

a plurality of first contact pads at a contact side of the first chip;

a plurality of second contact pads at the contact side of the first chip;

a second chip comprising a plurality of third contact pads at a contact side of the second chip; and

at least one first contact pad of the plurality of first contact pads of each of the plurality of first chips directly interconnected to at least one third contact pad of the plurality of third contact pads of the second chip;

at least one second contact pad of the plurality of second contact pads of each of the plurality of first chips of the first multi-chip module interconnected to at least one of the plurality of contact pads on the top side of the wiring board;

at least one second contact pad of the plurality of second contact pads of each of the plurality of first chips of the second multi-chip module interconnected to at least one of the plurality of contact pads on the bottom side of the wiring board;

a first plurality of direct connections respectively interconnected between the plurality of contact pads on the top side of the wiring board and the at least one second contact pad of the plurality of second contact pads of each of the plurality of first chips of the first multi-chip module;

a second plurality of direct connections respectively interconnected between the plurality of contact pads on the bottom side of the wiring board and the at least one second contact pad of the plurality of second contact pads of each of the plurality of first chips of second first multi-chip module; and

wherein the first plurality of direct connections and the second plurality of direct connections are longer than a thickness of the second chip of the first multi-chip module and the second multi-chip module, respectively.

2. The assembly according to claim 1, wherein the wiring board is an interposer.

3. The assembly according to claim 1, wherein at least one of the plurality of first chips of the first multi-chip module or the second multi-chip module comprises at least one of a sensor or an actuator, and the second chip of the first multi-chip module or the second multi-chip module, respectively, comprises a controller configured to either receive an electrical output provided by the sensor or to provide an electrical input to the actuator or both, through at least one interconnection of at least one of the plurality of third contact pads of the second chip associated with the controller to at least one of the first contact pads associated with the sensor or the actuator.

8. The apparatus according to claim 1, wherein the first multi-chip module and the second multi-chip module respectively comprise the first plurality of direct connections and the second plurality of direct connections.

9. The apparatus according to claim 8, wherein each of the first multi-chip module and the second multi-chip module comprise a molding material disposed along sides of the first plurality of direct connections and the second plurality of direct connections, respectively thereof.

10. The apparatus according to claim 9, wherein the first plurality of direct connections and the second plurality of direct connections respectively include first wire bonds and second wire bonds.

11. The apparatus according to claim 9, wherein the first plurality of direct connections and the second plurality of direct connections respectively include a first conductive material and a second conductive material respectively in holes defined in the molding material of each of the first multi-chip module and the second multi-chip module.

12. The apparatus according to claim 9, wherein the first plurality of direct connections and the second plurality of direct connections include solder lines, solder balls or stacks of solder balls.

13. The apparatus according to claim 1, wherein a non-contact side of the second chip of each of the first multi-chip module and the second multi-chip module is spaced apart from the top side and the bottom side, respectively, of the wiring board.

14. The apparatus according to claim 1, wherein the non-contact side of the second chip of each of the first multi-chip module and the second multi-chip module is spaced apart from the top side and the bottom side, respectively, of the wiring board leaving an airgap therebetween.

4. An apparatus for a microelectronic device, comprising:

an interposer comprising a plurality of pads at each of a top side and a bottom side thereof;

a first multi-chip module directly connected to the plurality of pads on the top side of the interposer;

a second multi-chip module directly connected to the plurality of pads on the bottom side of the interposer;

each of the first multi-chip module and the second multi-chip module comprising;

a first integrated circuit die having first contacts;

a second integrated circuit die and a third integrated circuit die each partially overlapping for the first multi-chip module and each partially underlapping for the second multi-chip module the first integrated circuit die respectively thereof; and

each of the second integrated circuit die and the third integrated circuit die having a first portion of second contacts coupled to the first contacts for electrical conductivity;

conductors at first ends thereof coupled to a second portion of the second contacts of each of the second integrated circuit die and the third integrated circuit die for electrical conductivity;

the conductors at second ends thereof opposite the first ends coupled to the pads of the interposer for electrical conductivity; and

the conductors having a height greater than a thickness of the first integrated circuit die for having the first integrated circuit die in a region between the conductors and between a surface portion of the interposer and corresponding facing surfaces of the second integrated circuit die and the third integrated circuit die with respect to the surface portion of the interposer.

5. The apparatus according to claim 4, wherein the conductors are wire bond wires.

6. The apparatus according to claim 4, wherein the conductors are a conductive material in holes defined in a molding material with an airgap between a surface of the molding material and facing surfaces of the second integrated circuit die and the third integrated circuit die.

7. The apparatus according to claim 4, wherein the conductors are solder lines, solder balls or stacks of solder balls.