Cu pillar bump with L-shaped non-metal sidewall protection structure

• US 10,163,837 B2
• Filed: 12/05/2016
• Issued: 12/25/2018
• Est. Priority Date: 05/18/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hwang, Chien Ling, Wu, Yi-Wen, Liu, Chung-Shi
• Primary Examiner(s): Vu, David
• Application Number:
  US15/368,936
• Publication Number:
  US 20170084563A1
• Time in Patent Office: 750 Days
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/10145 Flow barriers
• CPC Class Codes: H01L 2224/11019 for protecting parts during the process
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11464 Electroless plating
• CPC Class Codes: H01L 2224/11622 Photolithography
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13181 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/13552 : comprising protrusions or indentations
• CPC Class Codes: H01L 2224/13565 : Only outside the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13575 : Plural coating layers
• CPC Class Codes: H01L 2224/13686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/1369 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/814 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0504 : 14th Group
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/384 : Bump effects
• CPC Class Codes: H01L 2924/3841 : Solder bridging

Abstract

A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.

Claims

1. A method of forming an integrated circuit device, the method comprising:

forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure;

depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate;

removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure; and

bonding the bump structure to another die using a solder layer.

2. The method of claim 1, wherein removing the non-metal protection layer comprises performing an etching process to expose the top surface of the bump structure.

3. The method of claim 2, further comprising depositing a cap layer over the bump structure.

4. The method of claim 1, wherein removing the non-metal protection layer comprises:

forming a photoresist layer on the non-metal protection layer;

forming a first opening in the photoresist layer;

forming a second opening in the non-metal protection layer positioned corresponding to the first opening, thereby exposing the top surface of the bump structure; and

removing the photoresist layer.

5. The method of claim 1, wherein depositing the non-metal protection layer comprises depositing a silicon nitride layer, a polyimide layer, or combinations thereof.

6. The method of claim 1, wherein the forming of the bump structure comprises forming a conductive bump structure.

7. A method of forming an integrated circuit, the method comprising:

forming a copper layer over a substrate;

depositing a non-metal protective layer over a top surface of the copper layer and along sidewalls of the copper layer;

removing a portion of the non-metal protective layer over the top surface of the copper layer, wherein a top surface of the non-metal protective layer after removing the portion of the non-metal protective layer is above the top surface of the copper layer;

plating a cap layer over the top surface of the copper layer; and

plating a solder layer over the cap layer.

8. The method of claim 7, wherein removing the portion of the non-metal protective layer comprises planarizing the non-metal protective layer or etching the non-metal protective layer.

9. The method of claim 7, wherein the depositing of the non-metal protective layer comprises depositing the non-metal protective layer on a surface region of the substrate exposed by the copper layer.

10. The method of claim 7, wherein plating the cap layer is prior to depositing the non-metal protective layer.

11. The method of claim 7, wherein plating the cap layer occurs after depositing the non-metal protective layer.

12. The method of claim 7, wherein plating the solder layer occurs after depositing the non-metal protective layer.

13. The method of claim 7, further comprising depositing an under bump metallurgy (UBM) layer between the copper layer and the substrate, wherein the depositing of the non-metal protective layer comprises depositing the non-metal protective layer over sidewalls of the UBM layer.

14. A method of forming an integrated circuit, the method comprising:

depositing an under bump metallurgy (UBM) layer over a substrate;

plating a copper layer over the UBM layer;

depositing a non-metal protective layer over a top surface of the copper layer, along sidewalls of the copper layer, and along sidewalls of the UBM layer; and

removing a portion of the non-metal protective layer over the top surface of the copper layer, wherein a top surface of the non-metal protective layer after removing the portion of the non-metal protective layer is above the top surface of the copper layer.

15. The method of claim 14, wherein removing the portion of the non-metal protective layer comprises a planarization process.

16. The method of claim 14, wherein removing the portion of the non-metal protective layer comprises an etching process.

17. The method of claim 14, further comprising plating a solder layer over the copper layer.

18. The method of claim 17, wherein plating the solder layer comprises plating the solder layer prior to depositing the non-metal protective layer.

19. The method of claim 17, wherein depositing the non-metal protective layer comprises depositing the non-metal protective layer prior to plating the solder layer.

20. The method of claim 17, further comprising bonding the copper layer to a die using the solder layer.