Bump on pad (BOP) bonding structure in semiconductor packaged device

• US 10,163,839 B2
• Filed: 08/11/2017
• Issued: 12/25/2018
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Yao-Chun, Chuang, Chita, Kuo, Chen-Cheng, Chen, Chen-Shien
• Primary Examiner(s): Mazumder, Didarul
• Application Number:
  US15/675,264
• Publication Number:
  US 20170345783A1
• Time in Patent Office: 501 Days
• Field of Search: 257690, 257723-725, 257778, 257762, 257750, 257738, 257772, 257779-781, 257733, 257786, 257747, 257748, 257E2304, 257E21505, 257E23069, 257E2307
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05015 being circular or elliptic
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/141 Disposition
• CPC Class Codes: H01L 2224/16104 relative to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/814 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/81401 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/488 : consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

Claims

1. A package structure comprising:

an integrated circuit package comprising a conductive post, the conductive post having a first plan-view shape;

a substrate bonded to the integrated circuit package, the substrate comprising;

a first dielectric layer;

a first contact pad over the first dielectric layer, a bottom surface of the first contact pad being in physical contact with a topmost surface of the first dielectric layer, the first contact pad having a second plan-view shape, a line extending through a first center of the first plan-view shape and a second center of the second plan-view shape intersecting the first contact pad at an angle having less than 90 degrees, the first plan-view shape being a first racetrack shape and the second plan-view shape being a second racetrack shape; and

a second dielectric layer over the first contact pad and the first dielectric layer, the second dielectric layer being in physical contact with the topmost surface of the first dielectric layer; and

a solder layer extending through the second dielectric layer, the solder layer electrically and mechanically coupling the conductive post to the first contact pad.

2. The package structure of claim 1, wherein a long axis of the first racetrack shape is oriented toward a center of the integrated circuit package.

3. The package structure of claim 1, wherein the integrated circuit package further comprises:

a second contact pad; and

an under bump metallurgy (UBM) interposed between the second contact pad and the conductive post.

4. The package structure of claim 1, wherein a coefficient of thermal expansion (CTE) of the integrated circuit package is between about 2 ppm/°

C. and about 3 ppm/°

C., and wherein a coefficient of thermal expansion (CTE) of the substrate is about 17 ppm/°

C.

5. The package structure of claim 1, wherein an area of the first plan-view shape is less than an area of the second plan-view shape.

6. The package structure of claim 1, wherein a width of the second racetrack shape is between about 10 μ

m and about 10 μ

m.

7. The package structure of claim 1, wherein the substrate further comprises a routing line, the routing line being in electrical contact with the first contact pad.

8. A package structure comprising:

a die package comprising a conductive post, the conductive post having a first plan-view shape;

a substrate bonded to the die package, the substrate comprising;

a dielectric layer;

a contact pad over the dielectric layer, a bottom surface of the contact pad being in physical contact with a topmost surface of the dielectric layer, the contact pad having a second plan-view shape, a first center of the first plan-view shape being laterally spaced apart from a second center of the second plan-view shape, the first plan-view shape being a first racetrack shape and the second plan-view shape being a second racetrack shape; and

a solder resist layer over the contact pad and the dielectric layer, the solder resist layer being in physical contact with the topmost surface of the dielectric layer; and

a solder layer extending through the solder resist layer, the solder layer being in physical contact with the conductive post and the contact pad.

9. The package structure of claim 8, wherein the solder layer is in physical contact with a topmost surface of the solder resist layer.

10. The package structure of claim 8, wherein a coefficient of thermal expansion (CTE) of the substrate is greater than a CTE of the die package.

11. The package structure of claim 8, wherein the solder layer comprises:

a first portion in physical contact with the conductive post, the first portion having a first width; and

a second portion in physical contact with the contact pad, the second portion having a second width, the second width being different from the first width.

12. The package structure of claim 11, wherein the second width is less than the first width.

13. The package structure of claim 8, wherein a first surface area of the first racetrack shape is different from a second surface area of the second racetrack shape.

14. The package structure of claim 8, wherein a long axis of the first racetrack shape is oriented toward a center of the die package.

15. A package structure comprising:

a die package comprising a first conductive post and a second conductive post, the first conductive post being disposed at a first distance from a center of the die package, the second conductive post being disposed at a second distance from the center of the die package, the second distance being different from the first distance;

a substrate bonded to the die package, the substrate comprising;

a dielectric layer;

a first contact pad and a second contact pad over the dielectric layer, a bottom surface of the first contact pad being in physical contact with a topmost surface of the dielectric layer; and

a passivation layer over the first contact pad and the second contact pad, the passivation layer being in physical contact with the topmost surface of the dielectric layer;

a first solder layer extending through the passivation layer, the first solder layer electrically and mechanically coupling the first conductive post to the first contact pad, the first conductive post having a first plan-view shape, the first contact pad having a second plan-view shape, a center of the first plan-view shape being laterally spaced apart from a center of the second plan-view shape by a third distance, the first plan-view shape being a first racetrack shape and the second plan-view shape being a second racetrack shape; and

a second solder layer extending through the passivation layer, the second solder layer electrically and mechanically coupling the second conductive post to the second contact pad, the second conductive post having a third plan-view shape, the second contact pad having a fourth plan-view shape, a center of the third plan-view shape being laterally spaced apart from a center of the fourth plan-view shape by a fourth distance, the fourth distance being different from the third distance, the third plan-view shape being a third racetrack shape and the fourth plan-view shape being a fourth racetrack shape.

16. The package structure of claim 15, wherein the second distance is greater than the first distance.

17. The package structure of claim 16, wherein the fourth distance is greater than the third distance.

18. The package structure of claim 15, wherein a pitch between the first conductive post and the second conductive post is between about 30 μ

m and about 200 μ

m.

19. The package structure of claim 15, wherein a coefficient of thermal expansion (CTE) of the substrate is greater than a CTE of the die package.

20. The package structure of claim 15, wherein a first long axis of the first racetrack shape and a second long axis of the third racetrack shape are oriented toward the center of the die package.