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Apparatus containing circuit-protection devices

  • US 10,163,893 B1
  • Filed: 08/28/2017
  • Issued: 12/25/2018
  • Est. Priority Date: 08/28/2017
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • an array of memory cells;

    a plurality of data lines, each data line of the plurality of data lines connected to a respective set of memory cells of the array of memory cells;

    peripheral circuitry for access of the array of memory cells;

    a first transistor comprising a control gate, a first source/drain connected to the peripheral circuitry, and a second source/drain connected to a first data line of the plurality of data lines;

    a second transistor comprising a control gate, a first source/drain connected to the peripheral circuitry, and a second source/drain connected to a second data line of the plurality of data lines; and

    a third transistor comprising a control gate, a first source/drain connected to the second source/drain of the first transistor, and a second source/drain connected to a source of the array of memory cells; and

    a fourth transistor comprising a control gate, a first source/drain connected to the second source/drain of the second transistor, and a second source/drain connected to the second source/drain of the third transistor.

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