Apparatus containing circuit-protection devices

• US 10,163,893 B1
• Filed: 08/28/2017
• Issued: 12/25/2018
• Est. Priority Date: 08/28/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Michael
• Primary Examiner(s): Norman, James G
• Application Number:
  US15/687,732
• Time in Patent Office: 484 Days
• Field of Search: None
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

Apparatus including an array of memory cells may include circuit-protection devices that may include first and second circuit-protection units, a first gate having a first source/drain connected to a first node of the first circuit-protection unit, and a second gate having a first source/drain connected to a first node of the second circuit-protection unit, wherein a second source/drain of the first gate is connected to a second source/drain of the second gate.

Claims

1. An apparatus, comprising:

an array of memory cells;

a plurality of data lines, each data line of the plurality of data lines connected to a respective set of memory cells of the array of memory cells;

peripheral circuitry for access of the array of memory cells;

a first transistor comprising a control gate, a first source/drain connected to the peripheral circuitry, and a second source/drain connected to a first data line of the plurality of data lines;

a second transistor comprising a control gate, a first source/drain connected to the peripheral circuitry, and a second source/drain connected to a second data line of the plurality of data lines; and

a third transistor comprising a control gate, a first source/drain connected to the second source/drain of the first transistor, and a second source/drain connected to a source of the array of memory cells; and

a fourth transistor comprising a control gate, a first source/drain connected to the second source/drain of the second transistor, and a second source/drain connected to the second source/drain of the third transistor.

2. The apparatus of claim 1, wherein each data line of the plurality of data lines is selectively connected to its respective set of memory cells of the array of memory cells through a plurality of select gates.

3. The apparatus of claim 1, wherein the connections to the peripheral circuitry are selective connections.

4. The apparatus of claim 1, wherein the peripheral circuitry comprises circuitry selected from a group consisting of a data cache and a data register.

5. The apparatus of claim 1, further comprising:

a fifth transistor comprising a control gate, a first source/drain connected to the peripheral circuitry, and a second source/drain connected to a third data line of the plurality of data lines;

a sixth transistor comprising a control gate, a first source/drain connected to the peripheral circuitry, and a second source/drain connected to a fourth data line of the plurality of data lines;

a seventh transistor comprising a control gate, a first source/drain connected to the second source/drain of the fifth transistor, and a second source/drain connected to the source of the array of memory cells; and

an eighth transistor comprising a control gate, a first source/drain connected to the second source/drain of the sixth transistor, and a second source/drain connected to the second source/drain of the seventh transistor;

wherein the control gate of the first transistor and the control gate of the fifth transistor are commonly connected to a first control line;

wherein the control gate of the second transistor and the control gate of the sixth transistor are commonly connected to a second control line;

wherein the control gate of the third transistor and the control gate of the seventh transistor are commonly connected to a third control line; and

wherein the control gate of the fourth transistor and the control gate of the eighth transistor are commonly connected to a fourth control line.

6. The apparatus of claim 5, wherein the third control line comprises a spur forming a gate between the first source/drain of the third transistor and the first source/drain of the seventh transistor, and wherein the fourth control line comprises a spur forming a gate between the first source/drain of the fourth transistor and the first source/drain of the eighth transistor.

7. The apparatus of claim 6, wherein a corner between the third control line and its spur is rounded, and wherein a corner between the fourth control line and its spur is rounded.

8. The apparatus of claim 6, wherein the spur of the third control line extends over an isolation region between the first source/drain of the first transistor and the first source/drain of the fifth transistor, and wherein the spur of the fourth control line extends over an isolation region between the first source/drain of the second transistor and the first source/drain of the sixth transistor.

9. The apparatus of claim 8, wherein the first control line comprises a spur extending toward the spur of the third control line and over the isolation region between the first source/drain of the first transistor and the first source/drain of the fifth transistor, and wherein the second control line comprises a spur extending toward the spur of the fourth control line and over the isolation region between the first source/drain of the second transistor and the first source/drain of the sixth transistor.

10. The apparatus of claim 9, wherein a corner between the first control line and its spur is rounded, and wherein a corner between the second control line and its spur is rounded.

11. The apparatus of claim 5, wherein the third control line and the fourth control line are electrically connected.

12. The apparatus of claim 5, further comprising an isolation region between the first source/drain of the first transistor and the first source/drain of the fifth transistor, and an isolation region between the first source/drain of the second transistor and the first source/drain of the sixth transistor.