FETS and methods of forming FETS

• US 10,163,903 B2
• Filed: 08/14/2017
• Issued: 12/25/2018
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Liu, Chi-Wen, Wang, Chih-Hao
• Primary Examiner(s): Chin, Edward
• Application Number:
  US15/676,126
• Publication Number:
  US 20180026038A1
• Time in Patent Office: 498 Days
• Field of Search: 438283, 438197, 438440, 257E21409, 257E2154, 257E29001, 257E29081, 257E29242, 257E29255, 257327, 257328, 257401, 257 76, 257 77
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions

Abstract

A method includes forming a first semiconductor strip on a substrate, the first semiconductor strip including a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. A first portion of the first crystalline semiconductor material in first semiconductor strip is converted to a dielectric material, where a second portion of the first crystalline semiconductor material remains unconverted. Gate structures are formed over the first semiconductor strip and source/drain regions are formed on opposing sides of the gate structures.

Claims

1. A method comprising:

forming a first semiconductor strip, the first semiconductor strip comprising a substrate semiconductor material, a first crystalline semiconductor material above the substrate semiconductor material, and a second crystalline semiconductor material above the first crystalline semiconductor material, wherein the first crystalline semiconductor material is a different material from the second crystalline semiconductor material;

converting a first portion of the first crystalline semiconductor material to a first dielectric material, wherein after the converting the first portion of the crystalline semiconductor material step, a second portion of the first crystalline semiconductor material in the first semiconductor strip remains unconverted;

forming a gate structure over the first semiconductor strip; and

forming source/drain regions on opposing sides of the gate structure.

2. The method of claim 1, wherein converting the first crystalline semiconductor material comprises:

converting a portion of the second semiconductor material to a second dielectric material; and

converting a portion of the substrate semiconductor material to a third dielectric material.

3. The method of claim 2, further comprising:

removing the second dielectric material and the third dielectric material.

4. The method of claim 3, wherein a width of the first semiconductor strip is greater at a midpoint of the first dielectric material than at an interface of the first dielectric material and substrate semiconductor material.

5. The method of claim 1, further comprising:

depositing an isolation material on either side of the first semiconductor strip; and

recessing the isolation material so that a top surface of the isolation material is below a top surface of the second crystalline semiconductor material and above an interface of the second crystalline semiconductor material and first dielectric material.

6. The method of claim 5, wherein forming source/drain regions comprises:

recessing the first semiconductor strip adjacent the gate structure so that a top surface of first semiconductor strip is below a top surface of the isolation material; and

epitaxially growing a third crystalline semiconductor material in the recess.

7. The method of claim 1, wherein the portion of unconverted first crystalline semiconductor material in the first semiconductor strip is continuous from the substrate semiconductor material to the second crystalline semiconductor material.

8. The method of claim 1, wherein the first semiconductor strip is a part of an n-type FinFET.

9. A method comprising:

epitaxially growing a first crystalline semiconductor material on a substrate;

epitaxially growing a second crystalline semiconductor material above the first crystalline semiconductor material;

patterning the first crystalline semiconductor material and the second crystalline semiconductor material to form a first fin on the substrate;

oxidizing all of the first crystalline semiconductor material in the first fin to form a first oxide material, and oxidizing a portion of the second crystalline semiconductor material in the first fin to form a second oxide material;

forming isolation regions on the substrate and surrounding the first oxide material of the first fin;

forming a gate structure over the first fin and the isolation regions; and

forming source/drain regions on opposing sides of the gate structure.

10. The method of claim 9, comprising:

removing the second oxide material, reducing a width of the first fin.

11. The method of claim 9, wherein the fin includes a portion of the substrate.

12. The method of claim 11, wherein a width of the first fin is greater at a midpoint of the first oxide material than at an interface of the substrate portion of the first fin and the first oxide material.

13. The method of claim 9, wherein forming source/drain regions comprises:

recessing the first fin adjacent the gate structure so that a top surface of the first fin is below top surfaces of the isolation regions; and

epitaxially growing a third crystalline semiconductor material in the recess.

14. The method of claim 9, wherein the first fin is a part of a p-type FinFET.

15. A semiconductor device, comprising:

a first semiconductor strip disposed on a substrate;

a second semiconductor strip disposed on the substrate, wherein a channel region of the first semiconductor strip comprises;

a bottom portion disposed on the substrate comprising the same material as the substrate,

a middle portion comprising a first crystalline semiconductor material and a first oxide material, the first oxide material covering side portions of the first crystalline semiconductor material, and

a top portion comprising a second crystalline semiconductor material;

an isolation region disposed between the first semiconductor strip and the second semiconductor strip, the isolation region having a top surface which is lower than a top surface of the first semiconductor strip and higher than an interface of the second crystalline semiconductor material and the first crystalline semiconductor material in the first semiconductor strip; and

a gate structure formed over the channel region of the first semiconductor strip.

16. The semiconductor device, of claim 15, wherein a source/drain region of the first semiconductor strip further comprises:

a bottom portion disposed on the substrate comprising the same material as the substrate,

a middle portion comprising the first crystalline semiconductor material and the first oxide material, the first oxide material covering side portions of the first crystalline semiconductor material, and

a top portion comprising a third crystalline semiconductor material, the top portion extending above the isolation region.

17. The semiconductor device of claim 16, wherein the source/drain region of the first semiconductor strip further comprises:

an intermediate portion between the middle portion and the top portion, the intermediate portion comprising the second crystalline semiconductor material, wherein an interface between the intermediate portion and the top portion is below the top surface of the isolation region.

18. The semiconductor device of claim 15, wherein the first crystalline semiconductor material in the middle portion is continuous from the bottom portion to the top portion.

19. The semiconductor device of claim 15, wherein the first semiconductor strip and second semiconductor strip are part of an n-type FinFET.

20. The semiconductor device of claim 15, wherein the middle portion is wider at its widest point than the top portion at its widest point.