Array of conductive lines individually extending transversally across and elevationally over a mid-portion of individual active area regions

• US 10,163,908 B2
• Filed: 01/25/2016
• Issued: 12/25/2018
• Est. Priority Date: 07/23/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Karda, Kamal M., Mueller, Wolfgang, Dhir, Sourabh, Kerr, Robert, Hwang, Sangmin, Liu, Haitao
• Primary Examiner(s): Pizarro, Marcos D
• Application Number:
  US15/005,360
• Publication Number:
  US 20160155745A1
• Time in Patent Office: 1,065 Days
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1436 Dynamic random-access memory [DRAM]
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Claims

1. An array of recessed access gate lines and conductive lines, comprising:

active area regions having dielectric trench isolation material there-between, the trench isolation material comprising dielectric end projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions, the active area material being elevationally over the dielectric end projections, the trench isolation material comprising dielectric lateral projections extending laterally into opposing sides proximate the opposing ends under an elevationally outermost surface of the active area material proximate the opposing ends, the active area material being elevationally over the dielectric end projections proximate the opposing ends;

recessed access gate lines individually extending transversally across the active area regions and extending between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material; and

conductive lines individually extending transversally across and elevationally over a mid-portion of the individual active area regions, conductive material being directly against a mid-portion surface of the active area material of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover, the mid-portion surface being elevationally inward relative to the elevationally outermost surface of the active area material in the individual active area regions proximate the opposing ends.

2. An array of recessed access gate lines and conductive lines, comprising:

active area regions having dielectric trench isolation material there-between, the trench isolation material comprising dielectric end projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions, the active area material being elevationally over the dielectric end projections, the trench isolation material comprising dielectric lateral projections extending laterally into opposing sides proximate the opposing ends under an elevationally outermost surface of the active area material proximate the opposing ends, the active area material being elevationally over the dielectric end projections proximate the opposing ends;

recessed access gate lines individually extending transversally across the active area regions and extending between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material; and

conductive lines individually extending transversally across and elevationally over a mid-portion of the individual active area regions, conductive material being directly against a mid-portion surface of the active area material of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover, the individual active area regions being longitudinally elongated along a straight longitudinal axis, the mid-portion surface being laterally narrower perpendicular to the longitudinal axis than the elevationally outermost surfaces proximate the opposing ends.

3. An array of conductive lines, comprising:

active area regions having dielectric trench isolation material there-between, the trench isolation material comprising dielectric projections extending laterally into opposing sides proximate opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions proximate the opposing ends, the active area material being elevationally over the dielectric projections proximate the opposing ends; and

conductive lines individually extending transversally across and elevationally over a mid-portion of the individual active area regions, conductive material being directly against a mid-portion surface of the active area material of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover, the individual active area regions being longitudinally elongated along a straight longitudinal axis, the mid-portion surface being laterally narrower perpendicular to the longitudinal axis than the elevationally outermost surfaces proximate the opposing ends.

4. The array of claim 3 wherein the dielectric trench isolation material between the ends of immediately end-to-end adjacent active area regions comprises opposing sidewalls that taper laterally inward elevationally inward of furthest extents of the dielectric projections into the ends of those immediately end-to-end adjacent active area regions.

5. The array of claim 3 wherein the dielectric trench isolation material between the ends of immediately end-to-end adjacent active area regions comprises opposing sidewalls that are substantially vertical elevationally outward of furthest extents of the dielectric projections into the ends of those immediately end-to-end adjacent active area regions.

6. The array of claim 3 wherein projecting distance of the dielectric projections longitudinally into the respective ends is from about 5 to 10 nanometers from respective furthest longitudinal extents of the active area material.

7. The array of claim 3 wherein the dielectric projections start longitudinally projecting into the respective active area material ends at a depth of from about 10 to 20 nanometers from the elevationally outermost surface of the active area material.

8. An array of conductive lines, comprising:

active area regions having dielectric trench isolation material there-between, the trench isolation material comprising dielectric projections extending laterally into opposing sides proximate opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions proximate the opposing ends, the active area material being elevationally over the dielectric projections proximate the opposing ends; and

conductive lines individually extending transversally across and elevationally over a mid-portion of the individual active area regions, conductive material being directly against a mid-portion surface of the active area material of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover, the mid-portion surface being elevationally inward relative to the elevationally outermost surface of the active area material in the individual active area regions proximate the opposing ends.

9. The array of claim 8 wherein projecting distance of the respective dielectric projections laterally into the respective opposing sides is from about 5 to 10 nanometers from furthest lateral extents of the active area material.

10. The array of claim 8 wherein the dielectric projections start laterally projecting at from about 10 to 20 nanometers from the elevationally outermost surface of the active area material.

11. The array of claim 8 the dielectric trench isolation material between sides of immediately side-to-side adjacent active area regions comprises opposing sidewalls that taper laterally inward elevationally inward of furthest extents of the dielectric projections into the sides of those immediately side-to-side adjacent active area regions.

12. The array of claim 8 wherein the dielectric trench isolation material between the sides of immediately side-to-side adjacent active area regions comprises opposing sidewalls that are substantially vertical elevationally outward of furthest extents of the dielectric projections into the sides of those immediately side-to-side adjacent active area regions.

13. The array of claim 8 wherein the individual active area regions are longitudinally elongated along a straight longitudinal axis, the individual active area regions having their mid-portion surface laterally narrower perpendicular to the longitudinal axis than the elevationally outermost surfaces proximate the opposing ends.

14. A plurality of memory cells of memory circuitry incorporating the conductive lines of claim 8.

15. Memory circuitry according to claim 14 wherein the memory cells are DRAM cells individually comprising a capacitor.