Printable device wafers with sacrificial layers

• US 10,163,945 B2
• Filed: 01/08/2018
• Issued: 12/25/2018
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Bower, Christopher, Menard, Etienne, Meitl, Matthew, Carr, Joseph
• Primary Examiner(s): Henry, Caleb
• Application Number:
  US15/864,813
• Publication Number:
  US 20180130829A1
• Time in Patent Office: 351 Days
• Field of Search: 438700
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate

Abstract

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

Claims

1. A wafer comprising:

a substrate; and

a patterned sacrificial layer disposed on the substrate, the patterned sacrificial layer comprising an array of spaced-apart sacrificial patterns separated by anchors,

wherein the spaced-apart sacrificial portions can be substantially selectively etched by an etchant and the anchors are not substantially selectively etched by the etchant, and

wherein the anchors have a thickness that is entirely greater than or equal to a thickness of the spaced-apart sacrificial patterns between the spaced-apart sacrificial patterns.

2. The wafer of claim 1, comprising an array of devices, wherein each device is disposed entirely over one spaced-apart sacrificial portion.

3. The wafer of claim 2, wherein each of the devices is an integrated circuit device.

4. The wafer of claim 2, wherein each device is physically connected to at least one of the anchors by one or more respective tethers each laterally extending from a sidewall of the at least one of the anchors.

5. The wafer of claim 4, wherein each of the devices is attached to the one or more respective tethers over an attachment area having a height that is less than a height of the device.

6. The wafer of claim 2, wherein each of the devices is thicker than the spaced-apart sacrificial patterns.

7. The wafer of claim 2, wherein each of the devices is encapsulated by an inorganic capping layer and the capping layer comprises a metal or amorphous silicon.

8. The wafer of claim 2, wherein one or more devices in the array of devices has a roughened surface that is encapsulated by an inorganic capping layer.

9. The wafer of claim 2, comprising one or more multi-layer electrical interconnect networks, each of the multi-layer electrical interconnect networks disposed on a semiconductor active layer of a corresponding device of the array of devices, wherein one or more of the multi-layer electrical interconnect networks is encapsulated by an inorganic capping layer.

10. The wafer of claim 2, wherein the spaced-apart sacrificial patterns comprises at least one material selected from the group consisting of molybdenum, aluminum, copper, nickel, chromium, tungsten, titanium and alloys thereof.

11. The wafer of claim 1, wherein at least one of the anchors comprises polysilicon or an oxide.

12. The wafer of claim 1, wherein at least one of the anchors is ring shaped.

13. A wafer of devices comprising:

a substrate;

a sacrificial layer disposed on the substrate, wherein the sacrificial layer comprises an array of recesses;

an array of devices, each device of the array of devices laterally attached to at least one tether at least partially in a common layer with the device such that the device is suspended over a respective recess in the array of recesses with each of the at least one tether laterally extending from a sidewall of the respective recess, thereby defining a gap between the device and the substrate.

14. The wafer of claim 13, wherein the sacrificial layer comprises at least one material selected from the group consisting of molybdenum, aluminum, copper, nickel, chromium, tungsten, titanium and alloys thereof.

15. The wafer of claim 13, wherein each of the devices is attached to the at least one tether over an attachment area having a height that is less than a height of the device.

16. The wafer of claim 13, wherein each of the array of devices is thicker than the sacrificial layer.

17. The wafer of claim 13, wherein each of the devices is encapsulated by an inorganic capping layer and the capping layer comprises a metal or amorphous silicon.

18. The wafer of claim 13, wherein one or more of the devices has a roughened surface that is encapsulated by an inorganic capping layer.

19. The wafer of claim 13, comprising:

one or more multi-layer electrical interconnect networks, each of the multi-layer electrical interconnect networks disposed on a semiconductor active layer of a corresponding device of the array of devices, wherein one or more of the multi-layer electrical interconnect networks is encapsulated by an inorganic capping layer.

20. The wafer of claim 13, comprising:

a plurality of anchors disposed on the substrate in the sacrificial layer and separated by the recesses, wherein the sidewall of the respective recess is a portion of an anchor of the plurality of anchors.

21. The wafer of claim 20, wherein at least one of the plurality of anchors comprises polysilicon.