Pixel having an organic light emitting diode and method of fabricating the pixel

• US 10,163,996 B2
• Filed: 01/11/2017
• Issued: 12/25/2018
• Est. Priority Date: 02/24/2003
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Striakhilev, Denis, Nathan, Arokia, Vygranenko, Yuri, Tao, Sheng
• Primary Examiner(s): Guharay, Karabi
• Application Number:
  US15/403,313
• Publication Number:
  US 20170125498A1
• Time in Patent Office: 713 Days
• Field of Search: 313504, 313506, 313512
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 50/828 Transparent cathodes, e.g. comprising thin metal layers
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planarization dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less than 90 degrees to the TFT backplane. The via area and edges of an OLED bottom electrode pattern may be covered with a dielectric cap.

Claims

1. A pixel having a vertical architecture, comprising:

an organic light emitting diode (OLED) device having a bottom electrode, one or more OLED layers and a transparent top electrode for emitting light;

a thin-film transistor (TFT) based backplane for electrically driving the OLED device, the TFT based backplane being vertically integrated with the OLED layers and located below said bottom electrode to form a top-emitting OLED, the TFT based backplane comprising;

source and drain nodes; and

a thin conductive contact plate formed entirely on a flat portion of the pixel area and electrically coupled to a source or drain node, the thin conductive contact plate defined by a top surface, a bottom surface, and side surfaces, its vertical dimension defined by the top and bottom surfaces substantially smaller than its horizontal dimensions defined by the side surfaces;

a planarization dielectric layer provided between the TFT based backplane and the OLED bottom electrode so as to planarize the vertical profile on the TFT based backplane, said planarization dielectric layer being in direct contact with both said TFT based backplane and said OLED bottom electrode;

a via in said planarization dielectric layer to provide a communication path between said TFT based backplane and said OLED device and through said thin conductive contact plate; and

a dielectric layer deposited on top of said bottom electrode and covering said via and all the edges of said bottom electrode while leaving the rest of said bottom electrode uncovered.

2. The pixel as claimed in claim 1, wherein the sidewall of said via in the planarization layer is sloped against the TFT based backplane.

3. The pixel as claimed in claim 2, wherein the TFT based backplane includes:

a substrate;

an interlayer dielectric layer on the source and drain nodes; and

an interconnection plate patterned on a via of the interlayer dielectric layer and being connected to the source or drain node and the thin conductive contact plate;

wherein the planarization dielectric layer planarizes the vertical profile on the substrate with the fabricated TFT based backplane, and the sloped via providing the communication path through the interconnection plate.

4. The pixel as claimed in claim 3, wherein the thin conductive contact plate is formed on a flat portion of the interlayer dielectric layer such that the interconnection plate overlaps a part of the contact plate.

5. The pixel as claimed in claim 3, further comprising a shield electrode disposed between the planarization dielectric layer and the interlayer dielectric layer, which is located separately from the interconnection plate.

6. The pixel as claimed in claim 2, wherein the TFT based backplane includes:

a substrate;

wherein the thin conductive contact plate is formed such that the source or drain material overlaps the thin conductive contact plate and the planarization dielectric layer planarizes the vertical profile on the substrate with the fabricated TFT based backplane.

7. The pixel as claimed in claim 6, further comprising a shield electrode formed separately from said thin conductive contact plate.

8. The pixel as claimed in claim 1, in which said dielectric layer is patterned in such a way that it insulates the OLED layers from the OLED bottom electrode at pixel edges and in and around the via while leaving the rest of the OLED bottom electrode in the direct contact with the OLED layers.

9. The pixel as claimed in claim 8, wherein said dielectric layer includes polymer dielectric or inorganic insulator.

10. The pixel as claimed in claim 8, wherein said dielectric layer includes material selected from the group from BCB, polyimide, polymer dielectric, silicon nitride and a thin film inorganic.

11. The pixel as claimed in claim 1, wherein the pixel has a roughness of the order of 1 nm on the planarization dielectric layer and subsequent electrode layer.

12. The pixel as claimed in claim 1, further comprising continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer.

13. The pixel as claimed in claim 1, further comprising a shield electrode formed over the TFT.

14. The pixel as claimed in claim 1, wherein the planarization dielectric layer includes photosensitive benzocylobutene (BCB), the slope of the via being adjusted by the exposure time of the photosensitive BCB.

15. A method of fabricating a pixel, the pixel having an organic light emitting diode (OLED) bottom electrode, one or more OLED layers on the OLED bottom electrode, a transparent top electrode, and a thin-film transistor (TFT) based backplane for electrically driving the OLED and including a substrate, the method comprising the steps of:

providing the TFT based backplane on said substrate, including forming within the TFT based backplane a thin conductive contact plate entirely on a flat portion of the pixel area and electrically coupled to a source or drain node of the TFT based backplane, the thin conductive contact plate defined by a top surface, a bottom surface, and side surfaces, its vertical dimension defined by the top and bottom surfaces substantially smaller than its horizontal dimensions defined by the side surfaces;

providing a dielectric layer on the TFT based backplane, including the step of planarizing a vertical profile in the dielectric layer so as to planarize the vertical profile on the substrate with the TFT based backplane, said planarized dielectric layer being in direct contact with said TFT based backplane;

forming a via in said planarization dielectric layer to provide a communication path between said TFT based backplane and said OLED device and through said thin conductive contact plate;

depositing said OLED bottom electrode directly on top of said planarized dielectric layer and extending through said via into direct contact with said thin conductive contact plate of said TFT based backplane; and

depositing a dielectric layer on top of said bottom electrode and covering said via and all the edges of said bottom electrode while leaving the rest of said bottom electrode uncovered.

16. A method as claimed in claim 15, wherein forming said via which provides the communication path between the TFT backplane and the OLED device through the planarization dielectric layer, comprises forming the via such that the sidewall of the via in the planarization layer is sloped against the TFT based backplane.

17. A method as claimed in claim 15, wherein providing said dielectric layer between the OLED bottom electrode and the OLED layers, comprises patterning the dielectric layer in such a way that it insulates the OLED layers from the OLED bottom electrode at pixel edges and in and around the via while leaving the rest of the OLED bottom electrode in the direct contact with the OLED layers.

18. A method as claimed in claim 15, wherein the planarization dielectric layer including photosensitive benzocylobutene (BCB), further comprising the step of adjusting the exposure time of the photosensitive BCB such that the sidewall of the via in the planarization layer is sloped against the TFT based backplane.

19. A method as claimed in claim 15, wherein the pixel is formed such that the pixel has a roughness of the order of 1 nm on the planarization dielectric layer and subsequent electrode layer.

20. A method as claimed in claim 15, further comprising the step of providing continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer.

21. A method of fabricating a pixel, the pixel having an organic light emitting diode (OLED) bottom electrode, one or more OLED layers on the OLED bottom electrode, and a thin-film transistor (TFT) based backplane for electrically driving the OLED and including a substrate, the method comprising the steps of:

providing the TFT based backplane on said substrate, including forming within the TFT based backplane a thin conductive contact plate entirely on a flat portion of the pixel area and electrically coupled to a source or drain node of the TFT based backplane, the thin conductive contact plate defined by a top surface, a bottom surface, and side surfaces, its vertical dimension defined by the top and bottom surfaces substantially smaller than its horizontal dimensions defined by the side surfaces;

providing a dielectric layer on the TFT based backplane, including the step of planarizing a vertical profile in the dielectric layer so as to planarize the vertical profile on the substrate with the TFT based backplane, said planarized dielectric layer being in direct contact with said TFT based backplane;

forming a via in said planarization dielectric layer to provide a communication path between said TFT based backplane and said OLED device and through said thin conductive contact plate;

depositing said OLED bottom electrode directly on top of said planarized dielectric layer and extending through said via into direct contact with said thin conductive contact plate of said TFT based backplane, and

depositing a dielectric layer on top of said bottom electrode and covering said via and all the edges of said bottom electrode while leaving the rest of said bottom electrode uncovered.