FinFETs with strained well regions

• US 10,164,022 B2
• Filed: 08/28/2017
• Issued: 12/25/2018
• Est. Priority Date: 03/08/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Liu, Chi-Wen
• Primary Examiner(s): Lopez, Fei Fei Yeung
• Application Number:
  US15/688,214
• Publication Number:
  US 20170373190A1
• Time in Patent Office: 484 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 : for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/432 : Heterojunction gate for field effect devices
• CPC Class Codes: H01L 29/66431 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66787 : with a gate at the side of the channel
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/778 : with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/7789 : the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7842 : means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.

Claims

1. A device comprising:

a substrate;

insulation regions extending into the substrate;

a first semiconductor region between the insulation regions and having a first valence band, wherein the first semiconductor region comprises;

a first sub layer having a V-shaped bottom;

a second sub layer overlying the first sub layer, the second sub layer is doped with a p-type impurity; and

a third sub layer overlying the second sub layer;

a second semiconductor region over and adjoining the first semiconductor region, wherein the second semiconductor region has a second valence band higher than the first valence band; and

a semiconductor cap adjoining a top surface and sidewalls of the second semiconductor region, wherein the semiconductor cap has a third valence band lower than the second valence band.

2. The device of claim 1, wherein the semiconductor cap is intrinsic.

3. The device of claim 1, wherein the first sub layer and the third sub layer are intrinsic.

4. The device of claim 1, wherein the second semiconductor region comprises:

an upper portion higher than top surfaces of the insulation regions; and

a lower portion lower than the top surfaces of the insulation regions, wherein the upper portion and the lower portion are intrinsic, and the upper portion is narrower than the lower portion.

5. The device of claim 4, wherein a first sidewall of the upper portion, a top surface of the lower portion, and a sidewall of the lower portion form a step.

6. The device of claim 1 further comprising:

a gate dielectric over and in contact with the semiconductor cap;

a gate electrode over the gate dielectric; and

a source region and a drain region on opposite sides of and connected to the second semiconductor region, wherein the first semiconductor region and the second semiconductor region are between the source region and the drain region.

7. The device of claim 1, wherein the second semiconductor region comprises silicon germanium, and the semiconductor cap comprises silicon, and is free from germanium.

20. The device of claim 1, wherein the first semiconductor region is lower than a top surface of the insulation regions.

8. A device comprising:

a silicon substrate;

insulation regions extending into the silicon substrate;

a first silicon germanium region between the insulation regions and having a first germanium percentage, the first silicon germanium region comprises;

a first sub layer having a first p-type impurity concentration;

a second sub layer over and contacting the first sub layer, the second sub layer has a second p-type impurity concentration; and

a third sub layer over and contacting the second sub layer, the third sub layer has a third p-type impurity concentration, wherein the second p-type impurity concentration is higher than both the first p-type impurity concentration and the third p-type impurity concentration;

a second silicon germanium region over and adjoining the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage; and

a silicon-containing cap adjoining a top surface and sidewalls of the second silicon germanium region, wherein the silicon-containing cap has a third germanium percentage lower than the second germanium percentage.

9. The device of claim 8, wherein the first sub layer and the third sub layer are intrinsic, and the second sub layer comprises a p-type impurity.

10. The device of claim 8, wherein the second silicon germanium region comprises:

a lower portion comprising a top surface level with top surfaces of the insulation regions; and

an upper portion higher than the top surfaces of the insulation regions, wherein the upper portion is narrower than the lower portion, and a first sidewall of the upper portion, a top surface of the lower portion, and a sidewall of the lower portion form a step.

11. The device of claim 8, wherein the second silicon germanium region is intrinsic.

12. The device of claim 8, wherein the silicon-containing cap is free from germanium, and is intrinsic.

13. The device of claim 8, wherein the silicon-containing cap comprises silicon germanium, and is intrinsic.

14. The device of claim 8 further comprising:

a gate dielectric over and in contact with the silicon-containing cap;

a gate electrode over the gate dielectric; and

a source/drain region connected to the second silicon germanium region.

15. A device comprising:

a silicon germanium region having a first germanium percentage, the silicon germanium region comprises;

a first sub layer;

a second sub layer over and contacting the first sub layer, the second sub layer is doped with a p-type impurity; and

a third sub layer over and contacting the second sub layer, wherein the first sub layer and the third sub layer are free from p-type and n-type impurities;

a semiconductor fin overlapping the silicon germanium region, wherein the semiconductor fin comprises germanium; and

a silicon-containing cap adjoining a top surface and sidewalls of the semiconductor fin.

16. The device of claim 15, wherein the first sub layer, the second sub layer, and the third sub layer have a same germanium percentage.

17. The device of claim 15, wherein sidewalls of the silicon germanium region and sidewalls of the semiconductor fin are in different vertical planes that are parallel to each other.

18. The device of claim 15, wherein the semiconductor fin is free from p-type and n-type impurities.

19. The device of claim 15, wherein the silicon-containing cap is free from p-type and n-type impurities.