FinFETs with strained well regions

• US 10,164,023 B2
• Filed: 11/17/2017
• Issued: 12/25/2018
• Est. Priority Date: 03/08/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Liu, Chi-Wen, Wu, Cheng-Hsien, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Primary Examiner(s): Lopez, Fei Fei Yeung
• Application Number:
  US15/816,376
• Publication Number:
  US 20180083103A1
• Time in Patent Office: 403 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 : for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/432 : Heterojunction gate for field effect devices
• CPC Class Codes: H01L 29/66431 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66787 : with a gate at the side of the channel
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/778 : with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/7789 : the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7842 : means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Claims

1. A device comprising:

a Shallow Trench Isolation (STI) region;

a semiconductor region having a strain therein, wherein the semiconductor region comprises;

a wide portion having sidewalls contacting opposite sidewalls of the STI region; and

a narrow portion narrower than the wide portion overlapping the wide portion, wherein the narrow portion is higher than a top surface of the STI region to form a at least a first portion of a semiconductor fin;

a gate stack comprising a gate dielectric, wherein the semiconductor fin is located between opposite sidewall portions of the gate dielectric;

a source region and a drain region on opposite sides of the gate stack, wherein both the wide portion and the narrow portion extend from the source region to the drain region; and

a relaxed semiconductor region underlying the semiconductor region, wherein the relaxed semiconductor region extends into the STI region and has a first conduction band, and the semiconductor fin has a second conduction band lower than the first conduction band.

2. The device of claim 1, wherein the narrow portion is recessed from opposite sidewalls of the STI region toward a center line of the narrow portion.

3. The device of claim 1, wherein the wide portion and the narrow portion are formed of a same semiconductor material having same percentages of elements.

4. The device of claim 3, wherein the wide portion and the narrow portion are formed of silicon germanium, and a first germanium percentage in the wide portion is equal to a second germanium percentage in the narrow portion.

5. The device of claim 1, wherein the semiconductor region has a tensile strain.

6. The device of claim 1 further comprising a silicon cap between the semiconductor fin and the gate stack, wherein the silicon cap is free from n-type impurities.

20. The device of claim 1, wherein the gate stack, the source region, and the drain region form parts of an n-type Fin Field-Effect Transistor (FinFET).

7. A device comprising:

a silicon substrate;

an isolation region extending into the silicon substrate;

a first semiconductor region formed of a homogenous material, the first semiconductor region comprising;

a wide portion extending between portions of the isolation region; and

a narrow portion overlapping a portion of the wide portion, wherein the wide portion has a tensile stress therein;

an overlying layer contacting a top surface and sidewalls of the narrow portion and a top surface of the wide portion to form an interface;

a gate dielectric comprising;

a first portion overlapping a portion of the overlying layer; and

second portions connected to the first portion, wherein the narrow portion is between the second portions; and

a gate electrode having a bottom surface contacting a top surface of the gate dielectric.

8. The device of claim 7, wherein the overlying layer comprises a second semiconductor region, with both the first semiconductor region and the second semiconductor region comprising silicon germanium, and wherein the second semiconductor region has a lower germanium percentage than the first semiconductor region.

9. The device of claim 7, wherein the overlying layer has a sandwich structure comprising a top layer, a bottom layer, and a middle layer between the top layer and the bottom layer, and the middle layer has an n-type impurity concentration higher than n-type impurity concentrations of the top layer and the bottom layer.

10. The device of claim 9, wherein the top layer and the bottom layer are free from n-type impurities, and the top layer, the bottom layer, and the middle layer are formed of silicon germanium having a same germanium percentage.

11. The device of claim 7, wherein the first semiconductor region is free from n-type impurities.

12. The device of claim 7, wherein the first semiconductor region is further free from p-type impurities.

13. The device of claim 7 further comprising a source region and a drain region connected to opposite ends of the gate dielectric and the gate electrode, wherein both the wide portion and the narrow portion extend from the source region to the drain region.

19. The device of claim 7, wherein the first semiconductor region, the gate dielectric, and the gate electrode form parts of an n-type Fin Field-Effect Transistor (FinFET).

14. A device comprising:

Shallow Trench Isolation (STI) regions having a top surface;

a first semiconductor region located between portions of the STI regions, wherein the first semiconductor region is lower than the top surface of the STI regions, and wherein the first semiconductor region has first opposite sidewalk having a first distance from each other;

a second semiconductor region overlapping the first semiconductor region, wherein the second semiconductor region is higher than the top surface of the STI regions, wherein the second semiconductor region has second opposite sidewalls having a second distance smaller than the first distance, and the first semiconductor region and the second semiconductor region are formed of a same strained semiconductor material;

a third semiconductor region contacting a top surface and sidewalk of an upper portion of the second semiconductor region, wherein the third semiconductor region is formed of a semiconductor material different from the same strained semiconductor material;

a gate stack on the third semiconductor region; and

a source region and a drain region on opposite sides of the gate stack.

15. The device of claim 14, wherein the third semiconductor region comprises:

a first semiconductor layer free from at least one of n-type and p-type impurities; and

a second semiconductor layer doped with an n-type impurity over the first semiconductor layer.

16. The device of claim 15, wherein the first semiconductor layer is un-doped with n-type impurities.

17. The device of claim 16, wherein the first semiconductor layer is further un-doped with p-type impurities.

18. The device of claim 14, wherein the second opposite sidewalls extend from the source region to the drain region.