Method for manufacturing semiconductor structure

• US 10,164,046 B2
• Filed: 07/17/2017
• Issued: 12/25/2018
• Est. Priority Date: 12/17/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Primary Examiner(s): Au, Bac
• Application Number:
  US15/652,176
• Publication Number:
  US 20170317178A1
• Time in Patent Office: 526 Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2221/1042 the dielectric comprising air gaps
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas

Abstract

A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

Claims

1. A method for manufacturing a semiconductor structure, the method comprising:

forming a first dielectric layer on a gate structure and a source drain structure;

forming a recess at least partially in the first dielectric layer;

forming a protection layer at least on a sidewall of the recess;

deepening the recess to expose the source drain structure;

forming a bottom conductor in the recess, wherein;

the bottom conductor is electrically connected to the source drain structure, and

forming the bottom conductor comprises;

overfilling a conductive material in the recess; and

removing the conductive material and the first dielectric layer above the gate structure; and

forming a second dielectric layer on the gate structure;

forming an opening in the second dielectric layer to expose the bottom conductor and the protection layer; and

removing the protection layer through the opening to form a gap between the bottom conductor and the sidewall of the recess.

2. The method of claim 1, wherein the recess is deepened such that a portion of the first dielectric layer is left on the sidewall of the recess.

3. The method of claim 2, wherein the portion of the first dielectric layer left on the sidewall of the recess is between the gap and the source drain structure after the protection layer is removed.

4. The method of claim 1, further comprising:

forming an upper conductor in the opening, wherein the upper conductor is electrically connected to the bottom conductor.

5. The method of claim 1, wherein:

the protection layer is further formed on a bottom surface of the recess, and deepening the recess comprises;

removing a portion of the protection layer on the bottom surface of the recess.

6. The method of claim 1, further comprising:

forming an upper conductor in the opening, wherein the upper conductor is formed to cap a top opening of the gap.

7. The method of claim 1, wherein:

a hard mask is over the gate structure, and

the method further comprises;

after deepening the recess, removing a portion of the first dielectric layer over the hard mask to expose the hard mask.

8. The method of claim 1, further comprising:

forming the source drain structure above a substrate.

9. The method of claim 8, wherein forming the source drain structure comprises forming the source drain structure to contact a sidewall of a spacer adjacent to the gate structure.

10. The method of claim 1, wherein forming the recess comprises etching a spacer adjacent to the gate structure to form a tapered sidewall.

11. The method of claim 10, wherein forming the protection layer comprises forming the protection layer to contact the tapered sidewall of the spacer.

12. A method for manufacturing a semiconductor structure, the method comprising:

forming a first opening in a first dielectric layer to expose a source drain structure;

forming a protection layer on a sidewall of the first opening;

forming a bottom conductor in the first opening such that the bottom conductor is electrically connected to the source drain structure;

forming a second dielectric layer on the bottom conductor and the protection layer;

forming a second opening in the second dielectric layer to expose a top surface of the bottom conductor and a top surface the protection layer;

forming a gap around the bottom conductor by removing the protection layer through the second opening; and

forming an upper conductor on the bottom conductor, wherein the upper conductor is formed to cap a top opening of the gap.

13. The method of claim 12, wherein forming the upper conductor comprising:

overfilling a conductive material in the second opening; and

removing a portion of the conductive material exceeding the second opening.

14. The method of claim 12, wherein the protection layer comprises a nitride material.

15. The method of claim 12, wherein the first dielectric layer comprises a low-K dielectric material.

16. A method for manufacturing a semiconductor structure, the method comprising:

forming a first opening in a first dielectric layer to expose a source drain structure;

forming a protection layer on a sidewall of the first opening, wherein the first dielectric layer has a portion surrounding the protection layer;

forming a bottom conductor in the first opening such that the bottom conductor is electrically connected to the source drain structure;

etching back the portion of the first dielectric layer surrounding the protection layer to expose at least a portion of a sidewall of the protection layer;

forming a gap around the bottom conductor by removing the protection layer; and

forming an upper conductor on the bottom conductor, wherein the upper conductor is formed to cap a top opening of the gap.

17. The method of claim 16, wherein the protection layer comprises a nitride material.

18. The method of claim 16, wherein the first dielectric layer comprises a low-K dielectric material.

19. The method of claim 16, wherein forming the gap comprises forming the gap to expose the first dielectric layer.

20. The method of claim 16, wherein etching back the portion of the first dielectric layer comprises etching back the portion of the first dielectric layer such that a top surface of the bottom conductor is above a top surface of the first dielectric layer.