Devices including gate spacer with gap or void and methods of forming the same

• US 10,164,069 B2
• Filed: 02/26/2018
• Issued: 12/25/2018
• Est. Priority Date: 06/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Liu, Chi-Wen, Leung, Ying-Keung
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US15/905,177
• Publication Number:
  US 20180190796A1
• Time in Patent Office: 302 Days
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Claims

1. A semiconductor device comprising:

a gate stack over a semiconductor fin;

a first spacer with a first surface facing the gate stack and a second surface opposite the first surface, the second surface extending from a bottom of the first spacer to a top of the first spacer;

a second spacer with a third surface facing the second surface and a fourth surface opposite the third surface, the third surface extending from a bottom of the second spacer to a top of the second spacer, the top of the first spacer being planar with the top of the second spacer;

a conductive contact in physical contact with the fourth surface and in electrical contact with the semiconductor fin; and

a void extending from the second surface to the third surface.

2. The semiconductor device of claim 1, wherein a distance from the first surface to the fourth surface is between about 4 nm and about 10 nm.

3. The semiconductor device of claim 1, wherein the first spacer has a width of between about 1 nm and about 3 nm.

4. The semiconductor device of claim 1, wherein the void has a width of between about 2 nm and about 4 nm.

5. The semiconductor device of claim 1, wherein the second spacer has a width of between about 1 nm to about 3 nm.

6. The semiconductor device of claim 5, wherein the second spacer has a first height of between about 30 nm and about 80 nm.

7. The semiconductor device of claim 6, wherein the second spacer has a second height of between about 80 nm and about 130 nm.

8. A semiconductor device comprising:

a gas over a semiconductor fin;

a first dielectric material adjacent to the gas;

a second dielectric material adjacent to the gas opposite the first dielectric material;

a third dielectric material over the gas and extending between the first dielectric material and the second dielectric material, wherein the third dielectric material is different from the first dielectric material and the second dielectric material;

a gate stack in physical contact with the first dielectric material; and

a contact in physical contact with the second dielectric material, wherein at least a portion of an interface between the contact and the second dielectric material is straight.

9. The semiconductor device of claim 8, wherein the first dielectric material has a first height of between about 30 nm to about 80 nm.

10. The semiconductor device of claim 8, wherein a first aspect ratio of a combined width of the first dielectric material, the second dielectric material, and the third dielectric material and a first height of the first dielectric material is between about 3 and about 20.

11. The semiconductor device of claim 10, wherein a second aspect ratio of the combined width and a second height of the first dielectric material is between about 8 and about 33.

12. The semiconductor device of claim 11, wherein a third aspect ratio of a width of the third dielectric material to the first height is between about 7 and about 20.

13. The semiconductor device of claim 12, wherein a fourth aspect ratio of the third dielectric material to the second height is between about 20 and about 65.

14. The semiconductor device of claim 8, wherein the semiconductor fin is part of a 10 nm processing node.

15. A semiconductor device comprising:

a first surface over a semiconductor fin, the first surface comprising;

a first dielectric material;

a second dielectric material, different from and adjacent to the first dielectric material;

a third dielectric material different from and adjacent to the second dielectric material;

a fourth dielectric material different from and adjacent to the third dielectric material;

a first gate stack located between the fourth dielectric material and the semiconductor fin;

a void located between the second dielectric material and the semiconductor fin; and

a contact in electrical connection with the semiconductor fin, the first surface contacting the contact.

16. The semiconductor device of claim 15, wherein the first dielectric material has a first height of between about 30 nm and about 80 nm.

17. The semiconductor device of claim 16, wherein a height of the void is between about 0.3 times to about 0.7 times the first height.

18. The semiconductor device of claim 15, wherein the void extends below a top surface of the semiconductor fin.

19. The semiconductor device of claim 15, wherein the void does not extend below a top surface of the semiconductor fin.

20. The semiconductor device of claim 19, wherein the void exposes a fifth dielectric material.