Self-aligned passivation of active regions

• US 10,164,070 B2
• Filed: 06/25/2018
• Issued: 12/25/2018
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wann, Clement Hsingjen, Yeh, Ling-Yen, Shih, Chi-Yuan, Tsai, Wei-Chun
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US16/017,260
• Publication Number:
  US 20180308955A1
• Time in Patent Office: 183 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02065 the processing being a planarization of insulating layers
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Claims

1. A device comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate;

a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin comprises;

a top surface portion having a first concentration of a first passivation element, wherein the first passivation element is selected from sulfur (S), selenium (Se), and combinations thereof; and

an inner region having a second concentration of the first passivation element, wherein the second concentration is lower than the first concentration.

2. The device of claim 1, wherein the semiconductor fin further comprises a sidewall surface portion having a third concentration of the first passivation element, and the third concentration is lower than the first concentration.

3. The device of claim 2, wherein the semiconductor fin further comprises a corner surface portion connecting the top surface portion to the sidewall surface portion, wherein the corner surface portion has a fourth concentration of the first passivation element, and the fourth concentration is lower than the first concentration.

4. The device of claim 2, wherein:

the sidewall surface portion of the semiconductor fin further has a third concentration of a second passivation element; and

the inner region having a fourth concentration of the second passivation element, wherein the fourth concentration is lower than the third concentration.

5. The device of claim 4, wherein the second passivation element is different from the first passivation element, and the second passivation element is selected from antimony (Sb), sulfur (S), arsenic (As), and combinations thereof.

6. The device of claim 1, wherein the semiconductor fin further comprises:

a corner surface portion, wherein the corner surface portion has a third concentration of a second passivation element, and the second passivation element is selected from antimony (Sb), sulfur (S), arsenic (As), and combinations thereof; and

the inner region having a fourth concentration of the second passivation element, wherein the fourth concentration is lower than the third concentration.

7. The device of claim 6, wherein the corner surface portion has a surface on a (111) plane of the semiconductor fin.

8. The device of claim 6, wherein the second passivation element is different from the first passivation element.

9. A device comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate;

a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin comprises;

a top surface portion;

sidewall portions lower than the top surface portion, wherein the top surface portion and the sidewall portions comprise passivation elements selected from sulfur (S), selenium (Se), antimony (Sb), arsenic (As), and combinations thereof; and

an inner portion lower than the top surface portion and between the sidewall portions, wherein the inner portion has a lower concentration of the passivation elements than the top surface portion and the sidewall portions; and

a gate stack contacting the top surface portion and the sidewall portions.

10. The device of claim 9, wherein the top surface portion has a surface on a (001) plane of the semiconductor fin, and the sidewall portions have surfaces on (110) planes of the semiconductor fin.

11. The device of claim 9, wherein a first concentration of a first passivation element in the top surface portion is higher than a second concentration of the first passivation element in the sidewall portions, with the first passivation element being selected from sulfur (S) and selenium (Se).

12. The device of claim 9, wherein a third concentration of a second passivation element in the top surface portion is lower than a fourth concentration of the second passivation element in the sidewall portions, with the second passivation element being selected from sulfur (S), antimony (Sb), and arsenic (As).

13. The device of claim 9 further comprising a gate stack contacting the top surface portion and the sidewall portions of the semiconductor fin.

14. The device of claim 9, wherein the semiconductor fin further comprises a corner portion having a surface on a (111) plane of the semiconductor fin, and the corner portion comprises an addition passivation element selected from arsenic and chlorine, and an inner region of the semiconductor fin has a lower concentration of the addition passivation element than the corner portion.

15. The device of claim 14, wherein the addition passivation element is different from the passivation elements.

16. A device comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate; and

a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin comprises;

a top surface portion, wherein the top surface portion is doped with a first passivation element selected from sulfur and selenium; and

sidewall portion lower than, and connected to opposite ends of the top surface portion, wherein the sidewall portion is doped with a second passivation element selected from sulfur, antimony, and arsenic, and the second passivation element is different from the first passivation element.

17. The device of claim 16, wherein the semiconductor fin further comprises an inner portion lower than the top surface portion and on a side of the sidewall portion, wherein the inner portion has lower concentrations of the first and the second passivation elements than the top surface portion and the sidewall portion.

18. The device of claim 16 further comprising:

a gate dielectric contacting the top surface portion and the sidewall portion of the semiconductor fin; and

a gate electrode over a bottom portion of the gate dielectric.

19. The device of claim 16 further comprising a third passivation element in a corner surface portion of the semiconductor fin, with the third passivation element being selected from the group consisting of arsenic and chlorine, wherein the corner surface portion joins the sidewall portion to the top surface portion, and an inner region of the semiconductor fin has a lower concentration of the third passivation element than the top surface portion and the sidewall portion.

20. The device of claim 19, wherein the top surface portion has a surface on (001) plane, the sidewall portion has a surface on (110) plane, and the corner surface portion has a surface on (111) plane.