Self-aligned passivation of active regions
First Claim
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1. A device comprising:
- a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin comprises;
a top surface portion having a first concentration of a first passivation element, wherein the first passivation element is selected from sulfur (S), selenium (Se), and combinations thereof; and
an inner region having a second concentration of the first passivation element, wherein the second concentration is lower than the first concentration.
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Abstract
A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
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Citations
20 Claims
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1. A device comprising:
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a semiconductor substrate; isolation regions extending into the semiconductor substrate; a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin comprises; a top surface portion having a first concentration of a first passivation element, wherein the first passivation element is selected from sulfur (S), selenium (Se), and combinations thereof; and an inner region having a second concentration of the first passivation element, wherein the second concentration is lower than the first concentration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A device comprising:
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a semiconductor substrate; isolation regions extending into the semiconductor substrate; a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin comprises; a top surface portion; sidewall portions lower than the top surface portion, wherein the top surface portion and the sidewall portions comprise passivation elements selected from sulfur (S), selenium (Se), antimony (Sb), arsenic (As), and combinations thereof; and an inner portion lower than the top surface portion and between the sidewall portions, wherein the inner portion has a lower concentration of the passivation elements than the top surface portion and the sidewall portions; and a gate stack contacting the top surface portion and the sidewall portions. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A device comprising:
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a semiconductor substrate; isolation regions extending into the semiconductor substrate; and a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin comprises; a top surface portion, wherein the top surface portion is doped with a first passivation element selected from sulfur and selenium; and sidewall portion lower than, and connected to opposite ends of the top surface portion, wherein the sidewall portion is doped with a second passivation element selected from sulfur, antimony, and arsenic, and the second passivation element is different from the first passivation element. - View Dependent Claims (17, 18, 19, 20)
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Specification