Manufacturing method of semiconductor device including transistor

• US 10,164,075 B2
• Filed: 11/29/2017
• Issued: 12/25/2018
• Est. Priority Date: 07/15/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koezuka, Junichi, Okazaki, Kenichi, Kurosaki, Daisuke, Shima, Yukinori, Hosaka, Yasuharu
• Primary Examiner(s): Nguyen, Cuong Q
• Application Number:
  US15/825,153
• Publication Number:
  US 20180090602A1
• Time in Patent Office: 391 Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/02483 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film includes a first region in which an atomic proportion of In is larger than that of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). The second oxide semiconductor film includes a second region in which an atomic proportion of In is smaller than that of the first oxide semiconductor film. The second region includes a portion thinner than the first region.

Claims

1. A manufacturing method of a semiconductor device comprising a transistor, comprising:

forming a first oxide semiconductor film over a substrate;

forming a second oxide semiconductor film over the first oxide semiconductor film;

forming a source electrode and a drain electrode over the second oxide semiconductor film;

forming an oxide insulating film over the second oxide semiconductor film;

forming an oxide conductive film over the oxide insulating film;

adding oxygen into the oxide insulating film through the oxide conductive film; and

removing the oxide conductive film, and

wherein the step of forming the oxide insulating film is performed at a temperature higher than or equal to 180°

C. and lower than or equal to 350°

C. in a plasma enhanced chemical vapor deposition apparatus.

2. The manufacturing method of a semiconductor device, according to claim 1, wherein the temperature in the step of forming the oxide insulating film is the highest in the manufacturing steps of the transistor.

3. The manufacturing method of a semiconductor device, according to claim 1, wherein the first oxide semiconductor film and the second oxide semiconductor film each comprise oxygen, In, Zn, and M where M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

4. The manufacturing method of a semiconductor device, according to claim 1,

wherein the first oxide semiconductor film and the second oxide semiconductor film each comprise a crystal part, and

wherein the crystal part comprises a portion in which a c-axis of the crystal part is parallel to a normal vector of a surface on which the first oxide semiconductor film is formed or a normal vector of a surface on which the second oxide semiconductor film is formed.

5. A manufacturing method of a semiconductor device comprising a transistor, comprising:

forming a first oxide semiconductor film over a substrate;

forming a second oxide semiconductor film over the first oxide semiconductor film;

forming a source electrode and a drain electrode over the second oxide semiconductor film;

forming an oxide insulating film over the second oxide semiconductor film;

forming an oxide conductive film over the oxide insulating film;

adding oxygen into the oxide insulating film through the oxide conductive film; and

removing the oxide conductive film.

6. The manufacturing method of a semiconductor device, according to claim 5, wherein the temperature in the step of forming the oxide insulating film is the highest in the manufacturing steps of the transistor.

7. The manufacturing method of a semiconductor device, according to claim 5, wherein the first oxide semiconductor film and the second oxide semiconductor film each comprise oxygen, In, Zn, and M where M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

8. The manufacturing method of a semiconductor device, according to claim 5,

wherein the first oxide semiconductor film and the second oxide semiconductor film each comprise a crystal part, and

wherein the crystal part comprises a portion in which a c-axis of the crystal part is parallel to a normal vector of a surface on which the first oxide semiconductor film is formed or a normal vector of a surface on which the second oxide semiconductor film is formed.

9. A manufacturing method of a semiconductor device comprising a transistor, comprising:

forming a first oxide semiconductor film over a substrate;

forming a second oxide semiconductor film over the first oxide semiconductor film;

forming a source electrode and a drain electrode over the second oxide semiconductor film;

forming an oxide insulating film over the second oxide semiconductor film;

forming an oxide conductive film over the oxide insulating film; and

adding oxygen into the oxide insulating film through the oxide conductive film.

10. The manufacturing method of a semiconductor device, according to claim 9, wherein the temperature in the step of forming the oxide insulating film is the highest in the manufacturing steps of the transistor.

11. The manufacturing method of a semiconductor device, according to claim 9, wherein the first oxide semiconductor film and the second oxide semiconductor film each comprise oxygen, In, Zn, and M where M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

12. The manufacturing method of a semiconductor device, according to claim 9,

wherein the first oxide semiconductor film and the second oxide semiconductor film each comprise a crystal part, and

wherein the crystal part comprises a portion in which a c-axis of the crystal part is parallel to a normal vector of a surface on which the first oxide semiconductor film is formed or a normal vector of a surface on which the second oxide semiconductor film is formed.