Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure

• US 10,164,082 B2
• Filed: 03/22/2017
• Issued: 12/25/2018
• Est. Priority Date: 05/04/2012
• Status: Active Grant

• Current Assignee: Rensselaer Polytechnic Institute, UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Brueck, Steven R. J., Lee, Seung-Chang, Wetzel, Christian, Durniak, Mark
• Primary Examiner(s): Chin, Edward
• Application Number:
  US15/466,461
• Publication Number:
  US 20170194476A1
• Time in Patent Office: 643 Days
• Field of Search: 257 79, 257E33003, 257103, 257 14, 257 80, 257 95, 257 98, 257E21118, 257E21127, 257E21159, 257E21449, 257E21451, 257E31059, 257E33005, 257 33023, 257E33025, 257E33062, 257E33067, 257E33072, 257 13, 257189, 257200, 257615, 257627, 438 29, 438 22, 438 26, 438 46, 438 27, 438 28, 438285, 438 44, 438 47, 438478, 438481, 438604
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/24 : of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01S 5/021 : Silicon based substrates
• CPC Class Codes: H01S 5/22 : having a ridge or stripe structure
• CPC Class Codes: H01S 5/227 : Buried mesa structure ; Striped active layer
• CPC Class Codes: H01S 5/3203 : on non-planar substrates to create thickness or compositional variations
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

Claims

1. A method of forming a transistor, the method comprising:

providing a substrate comprising a first material portion and a single crystalline silicon layer on the first material portion, the substrate further comprising a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface exposing {111} faces of the single crystalline silicon layer;

depositing a buffer layer in one or more of the plurality of grooves;

epitaxially growing a semiconductor material over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase layer, one or both of the hexagonal crystalline phase layer and the cubic crystalline phase structure optionally being doped;

forming a gate of the transistor over the cubic crystalline phase structure, the gate comprising a gate electrode and an optional gate dielectric; and

forming a source contact and electrode and a drain contact and electrode of the transistor on the semiconductor material.

2. The method of claim 1, further comprising depositing an insulating layer on the major front surface of the substrate prior to depositing the buffer layer, patterning the insulating layer to expose stripes along <

011>

directions of the substrate, and forming the plurality of grooves in the exposed substrate regions, thereby exposing the {111} faces of the single crystalline silicon layer.

3. The method of claim 1, wherein one or more of the plurality of grooves are truncated v-grooves, each truncated v-groove comprising a first diagonal sidewall, a second diagonal sidewall opposing the first diagonal sidewall, and a bottom portion that is parallel with the major front surface of the substrate.

4. The method of claim 3, wherein during the epitaxially growing of the semiconductor material a gap is formed between the hexagonal crystalline phase layers and the bottom portion of the truncated v-groove.

5. The method of claim 1, further comprising removing at least a portion of the substrate and optionally removing at least a portion of the hexagonal crystalline phase layer.

6. The method of claim 5, wherein removing at least a portion of the substrate comprises removing the single crystalline silicon layer.

7. The method of claim 6, wherein the hexagonal crystalline phase layer is not removed, and further wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension decreasing with the height so that the structure is tapered, the hexagonal crystalline phase layer being adjacent to the tapered structure, the method optionally comprising doping at least one of the hexagonal crystalline phase layer and the cubic crystalline phase structure to form a source region, a drain region and a channel region.

8. The method of claim 7, further comprising etching the semiconductor material to expose a portion of the cubic crystalline material, forming a gate oxide over the cubic crystalline material, and forming a gate electrode over the gate oxide to form a MOS transistor, and optionally forming a backside contact.

9. The method of claim 8, wherein a depth of material removed from the height dimension of the cubic crystalline material during the etching determines a gate length of the transistor.

10. The method of claim 1, wherein epitaxially growing the semiconductor material comprises forming a heterojunction between the hexagonal crystalline phase layer and the cubic crystalline phase structure, the gate electrode being formed on the cubic crystalline phase structure to form a HEMT (“

high-electron-mobility transistor”

).

11. The method of claim 1, wherein epitaxially growing the semiconductor material comprises forming a heterojunction in the cubic crystalline phase structure, the gate electrode being formed on the cubic crystalline phase structure to form a HEMT (“

high-electron-mobility transistor”

).