Apparatus and method for power MOS transistor

• US 10,164,085 B2
• Filed: 03/21/2017
• Issued: 12/25/2018
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US15/464,423
• Publication Number:
  US 20170194483A1
• Time in Patent Office: 644 Days
• Field of Search: 257330
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/10 with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A method comprises forming a buried layer over a substrate, forming an epitaxial layer over the buried layer, forming a first trench and a second trench in the buried layer and the epitaxial layer, wherein a width of the second trench is greater than a width of the first trench, depositing a dielectric layer in the first trench and the second trench, wherein the dielectric layer partially fills the second trench, removing the dielectric layer in the second trench and forming a first gate region in the first trench and a second gate region in the second trench.

Claims

1. A method comprising:

forming an n-type buried layer over a p-type substrate;

forming an n-type epitaxial layer over the n-type buried layer;

forming a first trench and a second trench through the n-type epitaxial layer and partially through the n-type buried layer, wherein a width of the second trench is greater than a width of the first trench;

forming a dielectric region in the first trench, wherein a top surface of the dielectric region is higher than a top surface of the n-type buried layer, and a bottom surface of the dielectric region is lower than the top surface of the n-type buried layer;

forming a first gate region in the first trench and a second gate region in the second trench, wherein the first gate region is over the dielectric region; and

forming a source region and a drain region on opposite sides of the first trench, wherein the drain region is between the first trench and the second trench.

2. The method of claim 1, further comprising:

forming a p-type body region in the n-type epitaxial layer, wherein the p-type body region is a channel region and the source region is over the p-type body region.

3. The method of claim 1, further comprising:

applying a gate voltage to the first gate region and the second gate region; and

generating an accumulation layer along a sidewall of the second trench by attracting majority carriers.

4. The method of claim 3, wherein:

the accumulation layer provides a low resistance drain current path between the drain region and the n-type buried layer.

5. The method of claim 1, wherein:

the drain region is in contact with a sidewall of the second trench.

6. The method of claim 1, wherein:

the n-type buried layer is formed by a diffusion process, and wherein a doping density of the n-type buried layer is in a range from about 10¹⁹/cm³ to about 10²⁰/cm³.

7. The method of claim 1, wherein:

forming the first trench and the second trench comprises;

depositing a dielectric layer over the n-type epitaxial layer;

depositing a hard mask layer over the dielectric layer;

patterning the dielectric layer and the hard mask layer; and

applying an etching process to the n-type epitaxial layer and the n-type buried layer to form the first trench and the second trench.

8. The method of claim 7, wherein:

the dielectric layer is formed of oxide; and

the hard mask layer is formed silicon nitride.

9. The method of claim 1, wherein:

forming the dielectric region in the first trench comprises;

depositing a dielectric material to completely fill the first trench and partially fill the second trench; and

completely removing the dielectric material in the second trench and partially removing the dielectric material in the first trench, and wherein a remaining portion of the dielectric material in the first trench forms the dielectric region in the first trench.

10. The method of claim 1, further comprising:

prior to the step of forming the first gate region in the first trench and the second gate region in the second trench, forming a gate dielectric layer along sidewalls of the first trench and the second trench, over a top surface of the dielectric region and over a bottom of the second trench.

11. A method comprising:

forming a buried layer over a substrate;

forming an epitaxial layer over the buried layer;

depositing a dielectric layer over the epitaxial layer;

depositing a hard mask layer over the dielectric layer;

forming a first trench and a second trench through patterning the hard mask layer and the dielectric layer, wherein the first trench and the second trench are through the epitaxial layer and partially through the buried layer;

forming a dielectric region in the first trench, wherein a top surface of the dielectric region is higher than a top surface of the buried layer; and

forming a first gate region in the first trench and a second gate region in the second trench, wherein the first gate region is over the dielectric region.

12. The method of claim 11, further comprising:

after forming the first trench and the second trench and forming the dielectric region, removing the dielectric layer and the hard mask layer through an etching process.

13. The method of claim 11, wherein:

the first gate region and the second gate region are formed of poly-silicon.

14. The method of claim 11, further comprising:

forming a body region in the epitaxial layer;

forming a source region in the body region; and

forming a drain region in the epitaxial layer, and wherein the drain region and the source region on opposite sides of the first trench.

15. The method of claim 11, wherein:

a bottom of the first trench is substantially level with a bottom of the second trench; and

the bottom of the first trench is lower than a bottom of the epitaxial layer.

16. A method comprising:

forming a buried layer over a substrate;

forming an epitaxial layer over the buried layer;

forming a first trench and a second trench in the buried layer and the epitaxial layer, wherein a width of the second trench is greater than a width of the first trench;

depositing a dielectric layer in the first trench and the second trench, wherein the dielectric layer partially fills the second trench;

removing the dielectric layer in the second trench; and

forming a first gate region in the first trench and a second gate region in the second trench.

17. The method of claim 16, further comprising:

forming a body region in the epitaxial layer; and

forming a first drain/source region in the body region and a second drain/source region in the epitaxial layer, wherein;

the first drain/source region and the second drain/source region are formed on opposite sides of the first trench.

18. The method of claim 17, wherein:

the first drain/source region, the second drain/source region, the first gate region and the second gate region form a quasi-vertical transistor.

19. The method of claim 17, wherein:

the first drain/source region is a source region; and

the second drain/source region is a drain region, and wherein the drain region is between the first trench and the second trench.

20. The method of claim 16, wherein:

a bottom of the first trench is substantially level with a bottom of the second trench; and

a width of the second trench is greater than a width of the first trench.