Method and structure for FinFET devices
First Claim
1. A method, comprising:
- providing a semiconductor substrate that includes a first region containing a dopant of a first type and a second region containing a dopant of a second type that is opposite the first type;
forming a first layer on the first region and the second region, wherein the first layer contains a dopant of the second type;
recessing a portion of the first layer disposed over the first region;
forming a second layer on the recessed portion of the first layer disposed over the first region, wherein the second layer contains a dopant of the first type; and
performing a first Chemical Mechanical Planarization (CMP) process to planarize the first layer and the second layer.
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Abstract
A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.
28 Citations
20 Claims
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1. A method, comprising:
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providing a semiconductor substrate that includes a first region containing a dopant of a first type and a second region containing a dopant of a second type that is opposite the first type; forming a first layer on the first region and the second region, wherein the first layer contains a dopant of the second type; recessing a portion of the first layer disposed over the first region; forming a second layer on the recessed portion of the first layer disposed over the first region, wherein the second layer contains a dopant of the first type; and performing a first Chemical Mechanical Planarization (CMP) process to planarize the first layer and the second layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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providing a substrate having a first doped region and a second doped region of opposite dopant types; depositing a first semiconductor layer such that a first portion is on the first doped region and a second portion is on the second doped region; thinning the first portion of the first semiconductor layer; depositing a second semiconductor layer over the first portion of the first semiconductor layer; performing a first Chemical Mechanical Planarization (CMP) process to form a substantially planar surface including a topmost surface of the second semiconductor layer and a topmost surface of the second portion of the first semiconductor layer; and etching to form a first fin containing the first doped region, the first semiconductor layer, and the second semiconductor layer and to form a second fin containing the second doped region and the first semiconductor layer. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method comprising:
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providing a substrate having a first doped region of a first dopant type and a second doped region of a second dopant type that is opposite the first dopant type; forming a first semiconductor layer that includes a dopant of the second dopant type on the first doped region and the second doped region; recessing the first semiconductor layer over the first doped region; forming a second semiconductor layer that includes a dopant of the first dopant type over the first doped region; and etching to form a first set of fins containing the first doped region, the first semiconductor layer, and the second semiconductor layer and to form a second set of fins containing the second doped region and the first semiconductor layer. - View Dependent Claims (17, 18, 19, 20)
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Specification