Non-uniform superlattice structure
First Claim
Patent Images
1. A device, comprising:
- a semiconductor structure including a superlattice, wherein the superlattice includes;
a plurality of first semiconductor layers alternating with a plurality of second semiconductor layers, wherein at least one of;
a first semiconductor layer in the plurality of first semiconductor layers or a second semiconductor layer in the plurality of second semiconductor layers includes a plurality of regions including;
a fine structure region located only in an outer portion of the at least one of;
the first semiconductor layer or the second semiconductor layer, wherein the fine structure region includes a plurality of subscale features arranged in a growth direction, wherein the plurality of subscale features includes a plurality of subscale layers of a first band gap and a plurality of subscale layers of a second band gap, wherein the subscale layers of the first band gap alternate with the subscale layers of the second band gap, and wherein one of the subscale layers of the first band gap and the subscale layers of the second band gap include subscale layers of a plurality of distinct heights differing from each other.
0 Assignments
0 Petitions
Accused Products
Abstract
A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.
-
Citations
20 Claims
-
1. A device, comprising:
a semiconductor structure including a superlattice, wherein the superlattice includes; a plurality of first semiconductor layers alternating with a plurality of second semiconductor layers, wherein at least one of;
a first semiconductor layer in the plurality of first semiconductor layers or a second semiconductor layer in the plurality of second semiconductor layers includes a plurality of regions including;a fine structure region located only in an outer portion of the at least one of;
the first semiconductor layer or the second semiconductor layer, wherein the fine structure region includes a plurality of subscale features arranged in a growth direction, wherein the plurality of subscale features includes a plurality of subscale layers of a first band gap and a plurality of subscale layers of a second band gap, wherein the subscale layers of the first band gap alternate with the subscale layers of the second band gap, and wherein one of the subscale layers of the first band gap and the subscale layers of the second band gap include subscale layers of a plurality of distinct heights differing from each other.- View Dependent Claims (2, 3, 4, 5)
-
6. A device, comprising:
a semiconductor structure including a superlattice, wherein the superlattice includes; a plurality of first semiconductor layers alternating with a plurality of second semiconductor layers, wherein at least one of;
a first semiconductor layer in the plurality of first semiconductor layers or a second semiconductor layer in the plurality of second semiconductor layers includes a plurality of regions including;a fine structure region including a plurality of subscale features having a graded composition that varies in the growth direction, wherein the plurality of subscale features include a plurality of subscale barriers alternating with a plurality of subscale quantum wells. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
-
15. A device comprising:
a group III nitride semiconductor structure including a superlattice, wherein the superlattice includes; a plurality of first semiconductor layers alternating with a plurality of second semiconductor layers, wherein at least one of;
a first semiconductor layer in the plurality of first semiconductor layers or a second semiconductor layer in the plurality of second semiconductor layers includes a plurality of regions including;a fine structure region located only in an outer portion of the at least one of;
the first semiconductor layer or the second semiconductor layer, wherein the fine structure region includes a plurality of subscale layers having alternating compressive and tensile stresses, wherein the compressive and tensile stresses in the plurality of subscale layers decrease in a direction toward a first semiconductor layer-second semiconductor layer heterojunction adjacent to the outer portion.- View Dependent Claims (16, 17, 18, 19, 20)
Specification