Selective rasterization

• US 10,164,458 B2
• Filed: 04/20/2017
• Issued: 12/25/2018
• Est. Priority Date: 10/07/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Akenine-Moller, Tomas G., Munkberg, Carl J., Clarberg, Franz P.
• Primary Examiner(s): Buttram, Todd
• Application Number:
  US15/492,112
• Publication Number:
  US 20170256079A1
• Time in Patent Office: 614 Days
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: H02J 2207/40 adapted for charging from various sources, e.g. AC, DC or multivoltage
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.

Claims

1. A graphics processing unit comprising:

first circuitry to;

organize pixels, generated in response to execution in a draw call, into tiles;

determine whether a first tile processed after a second tile matches a characteristic of the second tile;

set a bit to indicate if characteristics of the first and second tiles match;

if the first tile matches the second tile based on the bit, forego rendering for the first tile;

if the first tile does not match the prior second tile, based on the bit, render the first tile; and

second circuitry to determine a hash for a third tile and a fourth tile, and if said hashes match, reduce processing of one of said third and fourth tiles.

2. The graphics processing unit of claim 1 said unit to receive a draw call and to set said bit based on said draw call.

3. The graphics processing unit of claim 1 said unit to set a single bit for each tile.

4. The graphics processing unit of claim 1 said unit to calculate a value for each tile based on data values that represent each tile.

5. A system comprising:

a graphics processing unit to;

organize pixels, generated in response to execution in a draw call into tiles;

determine whether a first tile processed after a second tile matches a characteristic of the second tile;

set a bit to indicate if characteristics of the first and second tiles match;

if the first tile matches the second tile based on the bit, forego rendering for the first tile;

if the first tile does not match the prior second tile, based on the bit, render the first tile;

determine a hash for a third tile and a fourth tile, and if said hashes match, reduce processing of one of said third and fourth tiles; and

a storage coupled to said graphics processing unit.

6. The system of claim 5 said unit to receive a draw call and to set said bit based on said draw call.

7. The system of claim 5 said unit to set a single bit for each tile.

8. The system of claim 5 said unit to calculate a value for each tile based on data values that represent each tile.

9. The system of claim 5 including a memory controller.

10. The system of claim 5 including a central processing unit.

11. The system of claim 5 including a display.

12. The system of claim 5 including a modem.

13. A method comprising:

organizing pixels, generated in response to execution in a draw call, into tiles;

determining whether a first tile processed after a second tile matches a characteristic of the second tile;

setting a bit to indicate if characteristics of the first and second tiles match;

if the first tile matches the second tile based on the bit, foregoing rendering for the first tile;

if the first tile does not match the prior second tile, based on the bit, rendering the first tile; and

determining a hash for a third tile and a fourth tile, and if said hashes match, reduce processing of one of said third and fourth tiles.

14. The method of claim 13 including receiving a draw call and to set said bit based on said draw call.

15. The method of claim 13 including setting a single bit for each tile.

16. The method of 13 including calculating a value for each tile based on data values that represent each tile.

17. One or more non-transitory computer readable media storing instructions to perform a sequence comprising:

organizing pixels, generated in response to execution in a draw call, into tiles;

determining whether a first tile processed after a second tile matches a characteristic of the second tile;

setting a bit to indicate if characteristics of the first and second tiles match;

if the first tile matches the second tile based on the bit, foregoing rendering for the first tile;

if the first tile does not match the prior second tile, based on the bit, rendering the first tile; and

determining a hash for a third tile and a fourth tile, and if said hashes match, reduce processing of one of said third and fourth tiles.

18. The media of claim 17, further storing instructions to perform a sequence including receiving a draw call and to set said bit based on said draw call.

19. The media of claim 17 including setting a single bit for each tile.

20. The method of 17 including calculating a value for each tile based on data values that represent each tile.