Composite integrated circuits and methods for wireless interactions therewith

• US 10,164,480 B2
• Filed: 05/08/2017
• Issued: 12/25/2018
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Min-Jer, Peng, Ching-Nen, Jou, Chewn-Pu, Kuo, Feng Wei, Chen, Hao, Lin, Hung-Chih, Chen, Huan-Neng, Yen, Kuang-Kai, Liu, Ming-Chieh, Lee, Tsung-Hsiung
• Primary Examiner(s): Tu, Christine T.
• Application Number:
  US15/589,435
• Publication Number:
  US 20170242071A1
• Time in Patent Office: 596 Days
• Field of Search: 714734, 714724, 714725, 714733, 455 41, 455558, 235492, 235487
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 2223/54446 Wireless electrical read out
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H02J 50/10 : using inductive coupling
• CPC Class Codes: H02J 50/20 : using microwaves or radio frequency waves
• CPC Class Codes: H02J 50/80 : involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices

Abstract

An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Claims

1. A device, comprising:

a first circuit layer comprising a wireless power transfer (WPT) device configured to extract energy from an electromagnetic signal and provide an output voltage;

a first chip electrically connected to the first circuit layer; and

a first tracking circuit disposed in the first chip, the first tracking circuit configured to be powered by the output voltage of the WPT device and to output tracking data in response to an instruction extracted from the electromagnetic signal.

2. The device of claim 1, wherein the first tracking circuit comprises:

a front end circuit electrically coupled with the WPT device;

a digital controller coupled with the front end circuit; and

a non-volatile memory coupled with the digital controller.

3. The device of claim 2, wherein the digital controller is configured to execute a circuit test in response to the instruction extracted from the electromagnetic signal.

4. The device of claim 1, further comprising an interconnection structure configured to electrically connect the WPT device and the first tracking circuit.

5. The device of claim 1, wherein the first chip is part of a chip package.

6. The device of claim 1, wherein the WPT device is electrically connected to a storage device.

7. The device of claim 1, wherein the device further comprises a second WPT device in the first chip.

8. The device of claim 1, wherein the device further comprises a second WPT device in the first circuit layer.

9. The device of claim 1, further comprising a second circuit layer, the second circuit layer comprising a second tracking circuit and a third chip, the second tracking circuit being in the third chip.

10. A method of outputting tracking data with a device, the method comprising:

generating, by a wireless power transfer (WPT) device of an integrated circuit (IC), an output voltage by extracting energy from an electromagnetic signal;

transmitting the output voltage from the WPT device to a first chip of the IC;

powering a tracking circuit in the first chip with the output voltage; and

with the tracking circuit, outputting tracking data of the first chip of the IC in response to an instruction extracted from the electromagnetic signal.

11. The method of claim 10, wherein the WPT is located within a second chip of the IC, and wherein transmitting the output voltage from the WPT device to the first chip of the IC comprises transmitting the output voltage from the second chip of the IC.

12. The method of claim 10, wherein

the WPT device is in a first circuit layer of the IC,

the first chip is in a second circuit layer of the IC, and

transmitting the output voltage comprises transmitting the output voltage from the first circuit layer of the IC to the second circuit layer of the IC.

13. The method of claim 10, further comprising, with the tracking circuit, storing a result of a known good die (KGD) test performed on the first chip.

14. The method of claim 10, further comprising executing a test on the IC.

15. The method of claim 10, further comprising selecting a second chip for adding to the IC based on the tracking data.

16. The method of claim 15, wherein the tracking data include a test result and selecting the second chip for adding to the IC based on the tracking data comprises selecting the second chip for adding to the IC based on the test result.

17. A method of testing a semiconductor structure, the method comprising:

causing a wireless power transfer (WPT) device of the semiconductor structure to generate an output voltage by extracting energy from an electromagnetic signal; and

executing a test of the semiconductor structure by using a tracking circuit embedded in a first chip of the semiconductor structure, the tracking circuit powered by the output voltage from the WPT device,

wherein the WPT device is embedded in a portion of the semiconductor structure.

18. The method of claim 17, wherein

the semiconductor structure is an integrated circuit (IC) comprising a first circuit layer and a second circuit layer, the second circuit layer comprising the first chip, and

the method further comprises:

selecting a second chip for adding to the IC based on a result of the test.

19. The method of claim 17, wherein

the semiconductor structure comprises a substrate under the first chip, and

the method further comprises:

transmitting the output voltage from the WPT device to the tracking circuit through an interconnection structure embedded in the substrate.

20. The method of claim 17, further comprising:

causing the semiconductor structure to execute another test of the semiconductor structure, the another test being powered by the output voltage from the WPT device, wherein

the another test is executed by using another tracking circuit embedded in the first chip or in a second chip.