Tank circuit and frequency hopping for isolators

• US 10,164,614 B2
• Filed: 03/31/2016
• Issued: 12/25/2018
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Yang, Xin, Zhao, Tianting, Chen, Baoxing
• Primary Examiner(s): Kinkead, Arnold
• Application Number:
  US15/087,723
• Publication Number:
  US 20170288650A1
• Time in Patent Office: 999 Days
• Field of Search: 331167, 331117 FE, 331 49, 331175
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H03B 2200/0072 Frequency hopping and enabling of rapid frequency changes
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03B 5/08 with frequency-determining element comprising lumped inductance and capacitance
• CPC Class Codes: H03B 5/12 active element in amplifier being semiconductor device H03B5/14 takes precedence
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1231 the amplifier comprising one or more bipolar transistors
• CPC Class Codes: H03B 5/1253 the transistors being field-effect transistors
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03B 5/1296 the feedback circuit comprising a transformer
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference

Abstract

Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

Claims

1. An oscillator circuit, comprising:

a tank circuit including;

an inductor having a first terminal and a second terminal, the inductor including a central tap coupled to a high reference voltage,

a first pair of transistors comprising;

a first transistor coupled between the first terminal of the inductor and a ground reference voltage along a source-to-drain path of the first transistor, and

a second transistor, coupled between the second terminal of the inductor and the ground reference voltage along a source-to-drain path of the second transistor,

a second pair of transistors comprising;

a third transistor, coupled along a source-to-drain path of the third transistor between a first gate of the first transistor and the ground reference voltage, and having a third gate configured to receive a control signal, and

a fourth transistor, coupled along a source-to-drain path of the fourth transistor between a second gate of the second transistor and the ground reference voltage, and having a fourth gate configured to receive the control signal,

wherein, in a first state, the control signal, in response to being received at the third and fourth gates, activates the second pair of transistors, and wherein the activation of the second pair of transistors is configured to deactivate the first pair of transistors and disable an oscillation of the oscillator circuit, and

a first pair of capacitors comprising;

a first capacitor coupled between the first inductor terminal and the second gate of the second transistor, and

a second capacitor, coupled between the second inductor terminal and the first gate of the first transistor.

2. The oscillator circuit of claim 1, wherein, in a second state, the control signal, in response to being received at the third and fourth gates, deactivates the second pair of transistors, the deactivation of the second pair of transistors being configured to activate the first pair of transistors and enable the oscillation of the oscillator circuit.

3. The oscillator circuit of claim 1, further comprising a control circuit configured to provide the control signal to the second pair of transistors.

4. The oscillator circuit of claim 1, wherein the first pair of transistors are DMOS transistors.

5. The oscillator circuit of claim 1, wherein the first pair of capacitors have substantially equal capacitances.

6. The oscillator circuit of claim 1, wherein the first pair of transistors are substantially the same size.

7. The oscillator circuit of claim 1, further comprising at least one sub-tank circuit including:

a third pair of transistors comprising;

a fifth transistor coupled between the first terminal of the inductor and the ground reference voltage along a source-to-drain path of the fifth transistor, and

a sixth transistor coupled between the second terminal of the inductor and the ground reference voltage along a source-to-drain path of the sixth transistor, and

a second pair of capacitors comprising;

a third capacitor coupled between the first inductor terminal and a sixth gate of the sixth transistor, and

a fourth capacitor coupled between the second inductor terminal and a fifth gate of the fifth transistor.

8. The oscillator circuit of claim 7, wherein the at least one sub-tank circuit further comprises a fourth pair of transistors comprising a seventh and eighth transistor, the seventh transistor coupled between the fifth gate of the fifth transistor and the ground reference voltage, the eighth transistor coupled between the sixth gate of the sixth transistor and the ground reference voltage;

wherein the seventh and eighth transistors have seventh and eighth gates, respectively, configured to receive a second control signal.

9. The oscillator circuit of claim 8, wherein, in a first state the second control signal, in response to being received at the seventh and eighth gates, activates the fourth pair of transistors, the activation of the fourth pair of transistors being configured to deactivate the third pair of transistors, and

in a second state, the second control signal, in response to being received at the seventh and eighth gates, deactivates the fourth pair of transistors, the deactivation of the fourth pair of transistors being configured to activate the third pair of transistors.

10. The oscillator circuit of claim 7, wherein the at least one sub-tank circuit further comprises a fourth pair of transistors comprising a seventh and eighth transistor, the seventh transistor coupled between the third capacitor and the sixth gate of the sixth transistor along a source-to-drain path of the seventh transistor, the eighth transistor coupled between the fourth capacitor and the fifth gate of the fifth transistor along a source-to-drain path of the eighth transistor, and the fourth pair of transistors having seventh and eighth gates, respectively, configured to receive a third control signal.

11. The oscillator circuit of claim 10, wherein, in a first state, the third control signal, in response to being received at seventh and eighth gates, activates the fourth pair of transistors, the activation of the fourth pair of transistors being configured to enable oscillation of the at least one sub-tank circuit, and

in a second state, the third control signal, in response to being received at the seventh and eighth gates, deactivates the fourth pair of transistors.

12. The oscillator circuit of claim 7, wherein the first pair and third pair of transistors are DMOS transistors and are substantially the same size.

13. The oscillator circuit of claim 1, wherein the inductor is a first winding of a transformer provided in a first circuit system, a second winding of the transformer provided in a second circuit system that is galvanically isolated from the first circuit system.

14. A method of operating a system having a first inductor-capacitor (LC) tank circuit and a second LC tank circuit in parallel with the first LC tank circuit, the method comprising:

activating a first pair of transistors of the first LC tank circuit comprising;

a first transistor coupled between a first terminal of an inductor and a ground reference voltage along a source-to-drain path of the first transistor, and

a second transistor coupled between a second terminal of the inductor and the ground reference voltage along a source-to-drain path of the second transistor, the inductor including a central tap coupled to a high reference voltage,

coupling, as a result of activating the first pair of transistors of the first LC tank circuit, the ground reference voltage to a pair of capacitors of the first LC tank circuit comprising;

a first capacitor coupled between the first inductor terminal and a second gate of the second transistor, and

a second capacitor coupled between the second inductor terminal and a first gate of the first transistor,

activating a first pair of transistors of the second LC tank circuit, the first pair of transistors of the second LC tank circuit comprising;

a third transistor coupled between the first terminal of the inductor and the ground reference voltage along a source-to-drain path of the third transistor, and

a fourth transistor coupled between the second terminal of the inductor and the ground reference voltage along a source-to-drain path of the fourth transistor,

wherein activating the first pair of transistors of the second LC tank circuit includes deactivating a second pair of transistors of the second LC tank circuit by applying a control signal to respective gates of the second pair of transistors of the second LC tank circuit, the second pair of transistors of the second LC tank circuit comprising a fifth and sixth transistor, the fifth transistor coupled between a first gate of the first transistor of the second LC tank circuit and the ground reference voltage, the sixth transistor coupled between a second gate of the second transistor of the second LC tank circuit and the ground reference voltage, and

coupling, as a result of activating the first pair of transistors of the second LC tank circuit, the ground reference voltage to a pair of capacitors of the second LC tank circuit, comprising;

a third capacitor coupled between the first inductor terminal and a fourth gate of the fourth transistor, and

a fourth capacitor coupled between the second inductor terminal and a third gate of the third transistor.

15. The method of claim 14, wherein activating the first pair of transistors of the first LC tank circuit includes deactivating a second pair of transistors of the first LC tank circuit by providing a second control signal to respective gates of the second pair of transistors of the first LC tank circuit, the second pair of transistors of the first LC tank circuit comprising:

a seventh transistor, coupled along a source-to-drain path of the seventh transistor between the first gate of the first transistor of the first LC tank circuit and the ground reference voltage, and

an eighth transistor, coupled along a source-to-drain path of the eighth transistor between the second gate of the second transistor of the first LC tank circuit and the ground reference voltage, and having an eighth gate configured to receive the second control signal.

16. A circuit, comprising:

means for activating a first pair of transistors, comprising a first transistor and a second transistor, of an inductor-capacitor (LC) tank, the first transistor coupled between a first terminal of an inductor and a ground reference voltage along a source-to-drain path of the first transistor, the second transistor coupled between a second terminal of the inductor and the ground reference voltage along a source-to-drain path of the second transistor, the inductor including a central tap coupled to a high reference voltage,

wherein the means for activating the first pair of transistors of the tank circuit includes means for deactivating a second pair of transistors of the tank circuit, the second pair of transistors of the tank circuit comprising;

a third transistor, coupled along a source-to-drain path of the third transistor between a first gate of the first transistor and the ground reference voltage, and having a third gate configured to receive a control signal and,

a fourth transistor, coupled along a source-to-drain path of the fourth transistor between a second gate of the second transistor and the ground reference voltage, and having a fourth gate configured to receive the control signal, and

a pair of capacitors, comprising a first capacitor and a second capacitor, of the tank circuit, the first capacitor coupled between the first inductor terminal and the second gate of the second transistor, the second capacitor coupled between the second inductor terminal and the first gate of the first transistor.

17. The circuit of 25, further comprising:

means for selectively activating one or more of a plurality of sub-tank circuits connected in parallel with the LC tank circuit at a first time instance.

18. The circuit of claim 17, wherein the means for selectivity activating the one or more sub-tank circuits includes:

means for activating a first pair of transistors of the sub-tank circuit, the first pair of transistors of the sub-tank circuit comprising;

a fifth transistor coupled between the first terminal of the inductor and the ground reference voltage along a source-to-drain path of the fifth transistor, and

a sixth transistor coupled between the second terminal of the inductor and the ground reference voltage along a source-to-drain path of the sixth transistor,

means for coupling, as a result of activating the first pair of transistors of the sub-tank circuit, a pair of capacitors of the sub-tank circuit, comprising;

a third capacitor coupled between the first inductor terminal and a sixth gate of the sixth transistor, and

a fourth capacitor coupled between the second inductor terminal and a fifth gate of the fifth transistor.

19. The circuit of claim 17, further comprising:

means for frequency hopping at a second time instance by selectively activating a different set of one or more of a plurality of sub-tank circuits.