Semiconductor device including DLL and semiconductor system

• US 10,164,645 B2
• Filed: 06/16/2017
• Issued: 12/25/2018
• Est. Priority Date: 12/01/2016
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Seo, Young-Suk, Im, Da-In
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/624,977
• Publication Number:
  US 20180159543A1
• Time in Patent Office: 557 Days
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H01Q 3/26 varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture H01Q3/12, H01Q3/22, H01Q3/24 take precedence
• CPC Class Codes: H03H 11/265 with adjustable delay
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Abstract

A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.

Claims

1. A semiconductor system comprising:

a controller configured to output an external clock signal and a command/address signal; and

a semiconductor device including;

a decoding unit configured to decode the command/address signal and generate an input control signal and an output control signal,

an initial value setting unit configured to sequentially store code values of a delay control signal in response to the input control signal when a locking signal is enabled, and select one of pre-stored code values of the delay control signal to output an initial value control signal in response to the output control signal, and

an internal clock generation unit configured to generate the delay control signal having an initial value that is set based on the initial value control signal, perform a locking operation of generating an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal, and output the locking signal and the delay control signal when the locking operation is finished.

2. The semiconductor system of claim 1, wherein the semiconductor device includes:

a delay locked loop (DLL) configured to delay the external clock signal by the predetermined time based on the delay control signal to output the internal clock signal.

3. The semiconductor system of claim 1, wherein the controller generates the command/address signal that includes frequency information on the external clock signal.

4. The semiconductor system of claim 1, wherein the initial value setting unit includes:

a control signal generator configured to generate a latch control signal based on the input control signal when the locking signal is enabled;

a preceding value storage including the plurality of the storages, and configured to sequentially store the delay control signal in the storages in response to each bit of the latch control signal; and

an initial value outputter configured to select one output of the storages to output the initial value control signal in response to the output control signal.

5. The semiconductor system of claim 4, wherein the control signal generator includes

a plurality of flip-flops serially coupled to each other, configured to receive the locking signal through a clock terminal, and the bits of the input control signal through a reset terminal, wherein an input terminal of a foremost flip-flop is coupled to a power source voltage terminal, and each bit of the latch control signal is outputted through an output terminal of each of the plurality of the flip-flops.

6. The semiconductor system of claim 1, wherein the internal clock generation unit includes:

a delay line configured to generate the internal clock signal by delaying the external clock signal in response to the delay control signal;

a delay compensator configured to generate a feedback clock signal by delaying the internal clock signal by a predetermined time;

a phase detector configured to generate a phase detection signal by comparing a phase of the external clock signal with a phase of the feedback clock signal; and

a delay controller configured to generate the delay control signal based on the phase detection signal, wherein the delay control signal is generated to have the initial value that is set based on the initial value control signal, and output the locking signal and the delay control signal when the locking operation is finished.

7. The semiconductor system of claim 1, wherein the internal clock generation unit is a digital delay locked loop.

8. A semiconductor device comprising:

a decoding unit configured to decode a command/address signal and generate an input control signal and an output control signal;

an initial value setting unit including a plurality of storages corresponding to bits of the input control signal, and configured to sequentially store code values of a delay control signal in the storages in response to the input control signal when a locking signal is enabled, and select one of the stored code values to output an initial value control signal based on the output control signal; and

a delay locked loop (DLL) configured to generate the delay control signal having an initial value that is set based on the initial value control signal, perform a locking operation of generating an internal clock signal by delaying an external clock signal based on the delay control signal, and output the locking signal and the delay control signal when the locking operation is finished.

9. The semiconductor device of claim 8, wherein the command/address signal includes frequency information on the external clock signal.

10. The semiconductor device of claim 8, wherein the initial value setting unit includes:

a control signal generator configured to generate a latch control signal based on the input control signal when the locking signal is enabled;

a preceding value storage including the plurality of the storages, and configured to sequentially store the delay control signal in the storages in response to each bit of the latch control signal; and

an initial value outputter configured to select one output of the storages to output the initial value control signal in response to the output control signal.

11. The semiconductor device of claim 10, wherein the control signal generator includes

a plurality of flip-flops serially coupled to each other, configured to receive the locking signal through a clock terminal, and the bits of the input control signal through a reset terminal, wherein an input terminal of a foremost flip-flop is coupled to a power source voltage terminal, and each bit of the latch control signal is outputted through an output terminal of each of the plurality of the flip-flops.

12. The semiconductor device of claim 8, wherein the delay locked loop includes:

a delay line configured to generate the internal clock signal by delaying the external clock signal in response to the delay control signal;

a delay compensator configured to generate a feedback clock signal by delaying the internal clock signal by a predetermined time;

a phase detector configured to generate a phase detection signal by comparing a phase of the external clock signal with a phase of the feedback clock signal; and

a delay controller configured to generate the delay control signal based on the phase detection signal, wherein the delay control signal is generated to have the initial value that is set based on the initial value control signal, and output the locking signal and the delay control signal when the locking operation is finished.

13. A semiconductor system comprising:

a controller configured to output an external clock signal, and an initial value control signal; and

a semiconductor device configured to generate a delay control signal having an initial value that is set based on the initial value control signal, and output an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal,

wherein the controller includes;

a processing unit configured to generate an input control signal and an output control signal based on frequency information of the external clock signal; and

an initial value setting unit including a plurality of storages corresponding to bits of the input control signal, and configured to receive a locking signal and the delay control signal from the semiconductor device, sequentially store code values of the delay control signal in the storages in response to the input control signal when the locking signal is enabled, and select one of the pre-stored code values to output the initial value control signal based on the output control signal.

14. The semiconductor system of claim 13, wherein the initial value setting unit includes:

a control signal generator configured to generate a latch control signal based on the input control signal when the locking signal is enabled;

a preceding value storage including the plurality of the storages, and configured to sequentially store the delay control signal in the storages in response to each bit of the latch control signal; and

an initial value outputter configured to select one output of the storages to output the initial value control signal in response to the output control signal.

15. The semiconductor system of claim 13, wherein the semiconductor device includes a digital delay locked loop.