Circuits for efficient detection of vector signaling codes for chip-to-chip communication

• US 10,164,809 B2
• Filed: 11/14/2017
• Issued: 12/25/2018
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Ulrich, Roger, Hunt, Peter
• Primary Examiner(s): Wong, Linda
• Application Number:
  US15/812,917
• Publication Number:
  US 20180069733A1
• Time in Patent Office: 406 Days
• Field of Search: 375219, 375220, 375221, 375222, 375229-236, 375240, 37524026, 37524027, 375254, 375257, 375259, 375285, 375295, 375316, 375318, 375317, 375319, 375340, 375346, 375350, 375351
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03426 transmission using multiple-input and multiple-output channels
• CPC Class Codes: H04L 2025/03789 Codes therefore
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Claims

1. A method comprising:

receiving a set of input signals via a corresponding set of wires of a multi-wire bus;

generating a differential output signal on a pair of differential output nodes using, in a first mode of operation, a set of input transistors driven by the set of input signals, the set of input transistors connected to the pair of differential output nodes for driving a combined differential current through the pair of differential output nodes, the set of input transistors connected to the corresponding set of wires according to an input permutation selected from plurality of input permutations associated with a vector signaling code;

generating, in a second mode of operation, the differential output signal using a pair of input transistors connected to a first pair of wires of the multi-wire bus, the pair of input transistors receiving a first pair of input signals of the sset of input signals via the first pair of wires of the multi-wire bus and responsively driving a differential current through the pair of differential output nodes; and

providing the differential output signal for use in determining an output bit.

2. The method of claim 1, wherein the first pair of wires of the multi-wire bus are adjacent.

3. The method of claim 1, further comprising attenuating the first pair of input signals in the second mode of operation.

4. The method of claim 1, wherein the pair of input transistors is part of the set of input transistors, and wherein one or more of the set of input transistors is disabled in the second mode of operation.

5. The method of claim 1, further comprising applying a bias to the set of input signals.

6. The method of claim 1, wherein the set of input signals corresponds to symbols of a codeword of the vector signaling code in the first mode of operation.

7. The method of claim 6, wherein the codeword is a permutation of ±

[+1, −

⅓

−

⅓

−

⅓

].

8. The method of claim 1, further comprising receiving a control signal to select between the first and second modes of operation.

9. The method of claim 8, wherein the control signal comprises a plurality of enable signals for selectively enabling a plurality of current sources connected to the set of input transistors.

10. The method of claim 1, wherein generating the differential output signal comprises drawing current through a differential pair of resistors connected to the pair of differential output nodes.

11. An apparatus comprising:

a set of input transistors configured to receive a set of input signals via a corresponding set of wires of a multi-wire bus and to responsively generate a differential output signal on a pair of differential output nodes, the set of input transistors configured to;

generate, in a first mode of operation, the differential output signal by driving a combined differential current through the pair of differential output nodes, the set of input transistors connected to the corresponding set of wires according to an input permutation selected from plurality of input permutations associated with a vector signaling code; and

generate, in a second mode of operation, the differential output signal by driving a differential current through a pair of the set of input transistors according to a first pair of input signals of the set of input signals received via a first pair of wires of the multi-wire bus; and

the pair of differential output nodes configured to provide the differential output signal for use in determining an output bit.

12. The apparatus of claim 11, wherein the first pair of wires of the multi-wire bus are adjacent.

13. The apparatus of claim 11, further comprising an attenuation circuit configured to attenuate the first pair of input signals in the second mode of operation.

14. The apparatus of claim 11, wherein one or more of the set of input transistors is disabled in the second mode of operation.

15. The apparatus of claim 11, further comprising a biasing circuit configured to apply a bias to the set of input signals.

16. The apparatus of claim 11, wherein the set of input signals correspond to symbols of a codeword of the vector signaling code in the first mode of operation.

17. The apparatus of claim 16, wherein the codeword is a permutation of ±

[+1, −

⅓

−

⅓

−

⅓

].

18. The apparatus of claim 11, wherein the set of input transistors is further configured to receive a control signal and to responsively select between the first and second modes of operation.

19. The apparatus of claim 18, wherein the set of input transistors are connected to a plurality of current sources, and wherein the control signal comprises a plurality of enable signals configured to selectively enable each current source.

20. The apparatus of claim 11, further comprising a differential pair of resistors connected to the pair of differential output nodes, the differential pair of resistors configured to generate the differential output signal as a differential voltage based on current drawn through the differential pair of resistors.