Method for manufacturing a micro electro-mechanical system

• US 10,167,191 B2
• Filed: 08/24/2017
• Issued: 01/01/2019
• Est. Priority Date: 04/04/2017
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: Kionix Incorporated (ROHM Co., Ltd.)
• Inventors: Heller, Martin, deWall, Jonah, Hocking, Andrew, Lynch, Kristin, Park, Sangtae
• Primary Examiner(s): Kusumakar, Karen
• Application Number:
  US15/685,957
• Publication Number:
  US 20180282154A1
• Time in Patent Office: 495 Days
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0242 Gyroscopes
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 3/001 Structures having a reduced contact area, e.g. with bumps or with a textured surface
• CPC Class Codes: B81C 1/00103 Structures having a predefined profile, e.g. sloped or rounded grooves
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2201/013 Etching
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2201/0171 Doping materials
• CPC Class Codes: B81C 2201/0178 Oxidation
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2201/0197 Processes for making multi-layered devices not provided for in groups B81C2201/0176 - B81C2201/0192
• CPC Class Codes: B81C 2201/05 Temporary protection of devices or parts of the devices during manufacturing
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/051 Active alignment, e.g. using internal or external actuators, magnets, sensors, marks or marks detectors

Abstract

A method of fabricating a semiconductor device, includes, in part, growing a first layer of oxide on a surface of a first semiconductor substrate, forming a layer of insulating material on the oxide layer, patterning and etching the insulating material and the first oxide layer to form a multitude of oxide-insulator structures and further to expose the surface of the semiconductor substrate, growing a second layer of oxide in the exposed surface of the semiconductor substrate, and removing the second layer of oxide thereby to form a cavity in which a MEMS device is formed. The process of growing oxide in the exposed surface of the cavity and removing this oxide may be repeated until the cavity depth reaches a predefined value. Optionally, a multitude of bump stops is formed in the cavity.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

growing a first layer of oxide on a surface of a first semiconductor substrate;

forming a layer of insulating material on the oxide layer;

patterning and etching the insulating material and the first oxide layer to form a plurality of oxide-insulator structures, said etching exposing the surface of the semiconductor substrate;

growing a second layer of oxide in the exposed surface of the semiconductor substrate; and

removing the second layer of oxide thereby to form a cavity in which the semiconductor device is formed.

2. The method of claim 1 further comprising:

growing a third layer of oxide on the exposed surface of the cavity; and

removing the third layer of oxide to increase the cavity depth.

3. The method of claim 2 further comprising:

repeating the growing of the third layer of oxide and removing the third layer of oxide until the cavity depth reaches a predefined value.

4. The method of claim 1 father comprising:

forming a plurality of bump stops in the cavity.

5. The method of claim 1 further comprising:

forming an oxide layer in the cavity.

6. The method of claim 1 further comprising:

placing an upper surface of a second semiconductor substrate above the first semiconductor substrate; and

bonding the first and second semiconductor substrates so as to seal the cavity between the first and second semiconductor substrates.

7. The method of claim 6 further comprising:

thinning the first semiconductor substrate.

8. The method of claim 7 further comprising:

forming a fourth layer of oxide on the outer surfaces of the first and second semiconductor substrates;

forming a trench in the first semiconductor substrate above the cavity; and

filling the trench with a fifth layer of oxide to form an isolation joint.

9. The method of claim 8 further comprising:

forming a contact opening in the fourth layer of oxide above the cavity.

10. The method of claim 9 further comprising:

forming a layer of screen oxide over the contact opening.

11. The method of claim 10 further comprising:

implanting dopants in the first semiconductor substrate through the screen oxide.

12. The method of claim 11 further comprising:

removing the screen oxide;

depositing a first layer of metal in the contact opening and over the fourth oxide layer adjacent the contact opening; and

depositing a first passivation layer over a portion of the first layer of metal.

13. The method of claim 12 further comprising:

forming first and second moats in the first semiconductor substrate, said first and second moats extending partially into the second semiconductor substrate; and

forming a plurality of fingers in the cavity of the first semiconductor substrate.

14. The method of claim 13 further comprising:

forming a first channel metal adjacent said first moat; and

forming a second channel metal adjacent said second moat.

15. The method of claim 14 further comprising:

forming a plurality of recesses in a third semiconductor substrate; and

kerf cutting the third semiconductor substrate.

16. The method of claim 15 further comprising:

forming a first layer metal on the third semiconductor substrate; and

patterning the first layer metal.

17. The method of claim 16 further comprising:

forming an oxide layer over the patterned first metal layer to form first and second bonding posts.

18. The method of claim 17 further comprising:

forming a metal getter in at least one of the recesses formed in the third semiconductor substrate.

19. The method of claim 18 further comprising:

forming a first contact between the first channel metal and the first bonding post;

forming a second contact between the second channel metal and the second bonding post; and

bonding the first semiconductor substrate to the second semiconductor substrate.

20. The method of claim 19 wherein said first, second and third semiconductor substrates are silicon substrates.

21. The method of claim 20 wherein said insulating material is silicon nitride.

22. The method of claim 20 wherein said metal getter includes Titanium.

23. The method of claim 19 further comprising:

frit bonding the first semiconductor substrate to the second semiconductor substrate.

24. The method of claim 1 wherein said semiconductor device is a MEMS device.