Liquid crystal display panel having dual capacitors connected in parallel to shift register unit and array substrate thereof
First Claim
1. An array substrate, comprising:
- a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body;
the first metal layer, the first dielectric layer, and the second metal layer forming a first capacitor;
the second metal layer, the insulating layer, and the electrode layer forming a second capacitor;
the electrode layer being connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel;
wherein the array substrate further comprises a thin-film transistor arranged on the substrate body and a shift register unit located at a non-display area, the first capacitor and the second capacitor are connected with the shift register unit in parallel, the thin-film transistor comprising a gate electrode, a source electrode, and a drain electrode, the gate electrode and the first metal layer are formed synchronously, the second metal layer and a source-drain electrode layer composed of the source electrode and the drain electrode are formed synchronously, the first dielectric layer of the first capacitor and the first dielectric layer provided between the source-drain electrode layer and the gate electrode are formed synchronously;
wherein the first capacitor and the second capacitor that are connected with the shift register unit are separate from the source electrode and the drain electrode of the thin-film transistor.
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Accused Products
Abstract
Disclosed are a liquid crystal display panel and an array substrate thereof. The array substrate includes a substrate body, a first metal layer, a first dielectric layer, and a second dielectric layer, an insulating layer, and an electrode layer. The first metal layer, the first dielectric layer, and the second metal layer form a first capacitor; the second metal layer, the insulating layer, and the electrode layer form a second capacitor; the electrode layer is connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel. Through the above way, the area of a gate driver on array (GOA) circuit on the array substrate can be reduced, which is beneficial for the narrow frame design of the liquid crystal display panel.
11 Citations
18 Claims
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1. An array substrate, comprising:
- a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body;
the first metal layer, the first dielectric layer, and the second metal layer forming a first capacitor;
the second metal layer, the insulating layer, and the electrode layer forming a second capacitor;
the electrode layer being connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel;wherein the array substrate further comprises a thin-film transistor arranged on the substrate body and a shift register unit located at a non-display area, the first capacitor and the second capacitor are connected with the shift register unit in parallel, the thin-film transistor comprising a gate electrode, a source electrode, and a drain electrode, the gate electrode and the first metal layer are formed synchronously, the second metal layer and a source-drain electrode layer composed of the source electrode and the drain electrode are formed synchronously, the first dielectric layer of the first capacitor and the first dielectric layer provided between the source-drain electrode layer and the gate electrode are formed synchronously; wherein the first capacitor and the second capacitor that are connected with the shift register unit are separate from the source electrode and the drain electrode of the thin-film transistor. - View Dependent Claims (2, 3, 4, 5)
- a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body;
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6. An array substrate, comprising:
- a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body;
the first metal layer, the first dielectric layer, and the second metal layer forming a first capacitor;
the second metal layer, the insulating layer, and the electrode layer forming a second capacitor;
the electrode layer being connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel;wherein the array substrate further comprises a shift register unit located at a non-display area, and the first capacitor and the second capacitor are connected with the shift register unit in parallel. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
- a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body;
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14. A liquid crystal display panel, comprising:
- a color film substrate arranged opposite to an array substrate, and a liquid crystal layer provided between the color film substrate and the array substrate, the array substrate comprising;
a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body;
the first metal layer, the first dielectric layer, and the second metal layer forming a first capacitor;
the second metal layer, the insulating layer, and the electrode layer forming a second capacitor;
the electrode layer being connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel;wherein the array substrate further comprises a shift register unit located at a non-display area, and the first capacitor and the second capacitor are connected with the shift register unit in parallel. - View Dependent Claims (15, 16, 17, 18)
- a color film substrate arranged opposite to an array substrate, and a liquid crystal layer provided between the color film substrate and the array substrate, the array substrate comprising;
Specification