Data storage device and data maintenance method thereof

• US 10,168,913 B2
• Filed: 06/09/2017
• Issued: 01/01/2019
• Est. Priority Date: 06/21/2016
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Chien-Cheng, Lee, Jie-Hao
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): Vo, Thanh D
• Application Number:
  US15/618,224
• Publication Number:
  US 20170364265A1
• Time in Patent Office: 571 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

Claims

1. A data storage device, comprising:

a flash memory, having a plurality of SLC (Single-Level Cell)-spare blocks, a plurality of TLC (Triple-Level Cell)-data blocks and a plurality of TLC-spare blocks; and

a controller, receiving a first data sector and a first logical address of the first data sector, writing the first data sector into a first TLC-spare block, and determining whether a first TLC-data block corresponding to the first logical address has valid data, wherein when the first TLC-data block has valid data, the controller further performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, deletes mapping relationships between the second logical address and the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

2. The data storage device as claimed in claim 1, wherein when the first TLC-data block does not have valid data, the controller maps the first TLC-spare block to the first logical address, and deletes a mapping relationship between the first logical address and the first TLC-data block.

3. The data storage device as claimed in claim 1, wherein the controller further determines whether the first logical address has valid data, when the first logical address has valid data, the controller further deletes mapping relationships between the first logical address and the TLC-data blocks which are mapped to the first logical address.

4. The data storage device as claimed in claim 1, wherein the controller writes the first data sector into a first SLC-spare block, a second SLC-spare block and a third SLC-spare block in the SLC-spare pool by an SLC storage mode, and writes the data stored in the first SLC-spare block, the second SLC-spare block and the third SLC-spare block into the first TLC-spare block by a TLC storage mode.

5. The data storage device as claimed in claim 1, wherein in a first stage, the controller writes a first sub-prewrite data sector, a second sub-prewrite data sector and a third sub-prewrite data sector of a prewrite data sector into the first TLC-data block, the second TLC-data block and the third TLC-data block by an SLC storage mode, and maps the first TLC-data block, the second TLC-data block and the third TLC-data block to the first logical address.

6. The data storage device as claimed in claim 5, wherein the first data sector and the first logical address is received by the controller in a second stage.

7. The data storage device as claimed in claim 6, wherein the first stage is a Production Phase, the second stage, which is after the first stage, is an Integration Phase, and the data storage device goes through a high-temperature soldering between the first stage and the second stage.

8. A data maintenance method, applied to a data storage device having a plurality of SLC (Single-Level Cell)-spare blocks, a plurality of TLC (Triple-Level Cell)-data blocks and a plurality of TLC-spare blocks, comprising:

receiving a first data sector and a first logical address of the first data sector, writing the first data sector into a first TLC-spare block;

determining whether a first TLC-data block corresponding to the first logical address has valid data;

when the first TLC-data block has valid data, performing a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block;

deleting mapping relationships between the second logical address and the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address; and

mapping the first TLC-spare block to the first logical address.

9. The data maintenance method as claimed in claim 8, further comprising:

when the first TLC-data block does not have valid data, mapping the first TLC-spare block to the first logical address, and deleting a mapping relationship between the first logical address and the first TLC-data block.

10. The data maintenance method as claimed in claim 8, further comprising:

determining whether the first logical address has valid data; and

when the first logical address has valid data, deleting mapping relationships between the first logical address and the TLC-data blocks which are mapped to the first logical address.

11. The data maintenance method as claimed in claim 8, wherein the step of writing the first data sector into the first TLC-spare block further comprises:

writing the first data sector into a first SLC-spare block, a second SLC-spare block and a third SLC-spare block in the SLC-spare pool by an SLC storage mode; and

writing the data stored in the first SLC-spare block, the second SLC-spare block and the third SLC-spare block into the first TLC-spare block by a TLC storage mode.

12. The data maintenance method as claimed in claim 8, wherein in a first stage the data maintenance method further comprises:

writing a first sub-prewrite data sector, a second sub-prewrite data sector and a third sub-prewrite data sector of a prewrite data sector into the first TLC-data block, the second TLC-data block and the third TLC-data block by an SLC storage mode; and

mapping the first TLC-data block, the second TLC-data block and the third TLC-data block to the first logical address.

13. The data maintenance method as claimed in claim 12, wherein the first data sector and the first logical address is received in a second stage.

14. The data maintenance method as claimed in claim 13, wherein the first stage is the Production Phase, the second stage, which is after the first stage, is the Integration Phase, and the data storage device goes through a high-temperature soldering between the first stage and the second stage.