Method for work scheduling in a multi-chip system

• US 10,169,080 B2
• Filed: 07/01/2016
• Issued: 01/01/2019
• Est. Priority Date: 03/07/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Kessler, Richard E., Snyder, II, Wilson P.
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US15/200,587
• Publication Number:
  US 20160314018A1
• Time in Patent Office: 914 Days
• Field of Search: 438107, 438108, 438109, 438110
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 2209/486 Scheduler internals
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5072 Grid computing

Abstract

According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.

Claims

1. A method of processing work items in a multi-chip system, the method comprising:

designating, by a work source component associated with a source chip device, a work item to a scheduler processor for scheduling, the source chip device being one of multiple chip devices of the multi-chip system, the work source component comprising a core processor or a coprocessor configured to create work items;

assigning, by the scheduler processor, the work item to a destination chip device of the multiple chip devices for processing, the scheduler processor being one of one or more scheduler processors each associated with a corresponding chip device of the multiple chip devices.

2. The method as recited in claim 1, wherein the method further includes:

receiving, by the work source component, a pointer to a work entry; and

sending, by the work source component, the pointer to the work entry to the scheduler processor of the one or more scheduler processors.

3. The method as recited in claim 1, wherein the method further includes:

creating, by the work source component, a work entry; and

sending, by the work source component, a pointer associated with the work entry to the scheduler processor of the one or more scheduler processors.

4. The method as recited in claim 1, wherein assigning the work item to the destination chip device of the multiple chip devices includes assigning the work item to a core processor of the one or more core processors associated with the chip device.

5. The method as recited in claim 1, wherein designating the work item includes designating all work items to a single scheduler processor configured to assign all work items from any work source component in the multi-chip system.

6. The method as recited in claim 1, wherein designating the work item includes selecting a scheduler processor of multiple scheduler processors associated with the multiple chip devices, each scheduler processor configured to assign work items to the multiple chip devices.

7. The method as recited in claim 6, wherein selecting a scheduler processor includes selecting a same scheduler processor for scheduling work items associated with a common work flow.

8. The method as recited in claim 6, wherein assigning the work item to a chip device of the multiple chip devices includes assigning the work item by the selected scheduler processor independently of other scheduler processors of the multiple scheduler processors.

9. The method as recited in claim 1, wherein the scheduler processor includes multiple scheduling queues for scheduling work items, and wherein designating the work item to a scheduler processor includes selecting a scheduling queue of the multiple scheduling queues for scheduling the work item.

10. The method as recited in claim 9, wherein selecting the scheduling queue includes:

maintaining a list of scheduling queues associated with the one or more scheduler processors; and

selecting the scheduling queue from the list maintained.

11. The method as recited in claim 1, wherein assigning a work item includes assigning work items associated with a common work flow to the same destination chip device.

12. The method as recited in claim 1, wherein the work item includes a processing operation associated with a data packet.

13. The method as recited in claim 1, wherein each chip device of the multiple chip devices includes a memory allocator, the method further comprising allocating memory, by one of the memory allocators, for storing data associated with the work item in one of the multiple chip devices.

14. The method as recited in claim 13, wherein allocating the memory includes allocating the memory for storing the work item in the first chip device to which the work item is assigned.

15. The method as recited in claim 13, wherein allocating the memory includes:

maintaining a list of memory buffers associated with the multiple chip devices for storing data associated with a work item; and

allocating a memory buffer for storing the data associated with the work item based on the list maintained.

16. The method as recited in claim 1, wherein assigning a work item to a destination chip device includes forwarding by a first scheduler processor residing in a first chip device the work item to a second scheduler processor located in the destination chip device, the destination chip device is different from the first chip device.

17. The method as recited in claim 16, wherein forwarding the work item includes forwarding the work item through a communications channel designated to carry communications between coprocessors in the first chip device and coprocessors in the destination chip device.