Non-volatile memory including selective error correction

• US 10,169,144 B2
• Filed: 01/15/2016
• Issued: 01/01/2019
• Est. Priority Date: 01/15/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Christensen, Carla L.
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US14/997,164
• Publication Number:
  US 20170206131A1
• Time in Patent Office: 1,082 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

Claims

1. An apparatus comprising:

a first memory area included in a memory device and a second memory area included in the memory device, the first and second memory area selectively coupled to each other through a conductive path in the memory device; and

control circuitry included in the memory device to communicate with a memory controller, the memory controller including an error correction engine, the control circuitry of the memory device configured to retrieve first information stored in the first memory area and store the first information after the error correction engine performs an error detection operation on the first information, and to retrieve second information stored in the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information such that the error correction engine skips performing an additional error detection operation on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

2. The apparatus of claim 1, wherein the control circuitry is configured to store the second information in the second memory area without the additional error detection operation performed on the second information if the result from the error detection operation performed on the first information indicates no error is detected in first information.

3. The apparatus of claim 1, wherein the control circuitry is configured to store the second information in the second memory area without the additional error detection operation performed on the second information if the result from the error detection operation performed on the first information indicates an error is detected in the first information and an error value of the error is not greater than a threshold value.

4. The apparatus of claim 1, wherein the first memory area includes first memory cells, the second memory area includes second memory cells, each of the first memory cells is configured to store at least one bit of information, and each of the second memory cells is configured to store more than one bit of information.

5. The apparatus of claim 1, wherein the first memory area includes memory cells organized into memory units, each of the memory units is configured to store pages of information, the first information and the second information are retrieved from a selected memory unit among the memory units, and the first information includes fewer than all pages in the selected memory unit.

6. The apparatus of claim 1, wherein the first memory area includes memory cells organized into memory units, and the first information and the second information are retrieved from a same memory unit among the memory units.

7. The apparatus of claim 6, wherein the second memory area includes memory cells organized into memory units, and the first information and the second information are stored in a same memory unit among the memory units of the second memory area after the first information and the second information are retrieved from the first memory area.

8. The apparatus of claim 1, wherein the first information includes a first portion and a second portion, the first portion is stored in the first memory area before the second portion is stored in the first memory area.

9. The apparatus of claim 8, wherein the second information is stored in the first memory area after the first portion of the first information is stored in the first memory area and before the second portion of the first information is stored in the first memory area.

10. The apparatus of claim 1, wherein retrieving the first information and the second information is performed during a memory management operation to move information from at least one memory unit in the first memory area to at least one memory unit in the second memory area.

11. An apparatus comprising:

a memory controller to communicate with a memory device, the memory controller including an error correction engine, the memory controller configured to;

use the error correction engine to perform an error detection operation on first information stored in a first memory area of the memory device to detect any errors in the first information and to determine whether detected errors meet a threshold condition after the error detection operation;

store the first information in a second memory area of the memory device after the error detection operation;

skip performing an additional error detection operation on second information if a result from the error detection operation performed on the first information meets a threshold condition; and

provide an indication to the memory device to allow the memory device to retrieve the second information from the first memory area and store the second information in the second memory area.

12. The apparatus of claim 11, wherein the memory controller is configured to provide the indication to the memory device if the result from the operation performed on the first information indicates no error is detected in the first information.

13. The apparatus of claim 11, wherein the memory controller is configured to provide the indication to the memory device if the result from the error detection operation indicates an error is detected in the first information and an error value of the error is not greater than a threshold value.

14. The apparatus of claim 11, wherein the error correction engine is configured to correct the error in the first information before providing the first information to the memory device to be stored in the second memory area of the memory device.

15. The apparatus of claim 11, wherein the first memory area includes first memory cells, the second memory area includes second memory cells, each of the first memory cells is configured to store at least one bit of information, and each of the second memory cells is configured to store up to multiple bits of information.

16. The apparatus of claim 11, wherein the memory controller is configured to receive the first information during an operation of moving information from the first memory area of the memory device to the second memory area of the memory device without receiving a command from a host to retrieve the first information from the first memory area.

17. An apparatus comprising:

a memory device including first memory cells and second memory cells, each of the first memory cells configured to store at least one bit of information, each of the second memory cells configured to store up to multiple bits of information; and

a memory controller coupled to the memory device, the memory controller including an error correction engine, the memory controller configured to use the error correction engine to perform an operation to determine whether first information retrieved from the first memory cells has an error, to skip performing an additional error detection operation on second information based on a result of the operation performed on the first information, and to allow the memory device to retrieve the second information from the first memory cells and store the second information in the second memory cells.

18. The apparatus of claim 17, wherein the memory controller is configured to allow the memory device to store the second information in the second memory cells without determining whether the second information has an error if the result indicates no error is detected in the first information.

19. The apparatus of claim 17, wherein the memory controller is configured to allow the memory device to store the second information in the second memory cells without determining whether the second information has an error if the result indicates an error is detected in the first information and an error value of the error is not greater than a threshold value.

20. The apparatus of claim 17, wherein the first memory cells are organized into a first block and a second block, and the first information and the second information are stored in the first block.

21. The apparatus of claim 17, wherein the memory controller is located on a die and the memory device is located on the die.

22. The apparatus of claim 17, wherein the memory controller is located on a first die and the memory device is located on a second die.

23. An apparatus comprising:

a host; and

a solid state drive (SSD) including non-volatile memory cells, the SSD including a host interface coupled to the host, a memory controller coupled to the host interface, memory controller including an error correction engine, and a memory device coupled to the memory controller, the memory device including a first memory unit and a second memory unit, the first memory unit including first memory cells, the second memory unit including second memory cells, each of the first memory cells configured to store at least one bit of information, each of the second memory cells configured to store up to multiple bits of information, the memory controller configured to use the error correction engine to perform an operation to determine whether first information retrieved from the first memory cells has an error, to skip performing an additional error detection operation on second information based on a result of the operation performed on the first information, and to allow the memory device to retrieve the second information from the first memory cells and store the second information in the second memory cells.

24. The apparatus of claim 23, wherein the memory device is configured to store the second information in the second memory cells without determining whether the second information has an error if the result indicates no error is detected in the first information.

25. The apparatus of claim 23, wherein the memory device is configured to store the second information in the second memory cells without determining whether the second information has an error if the result indicates an error is detected in the first information, and an error value of the error is not greater than a threshold value.

26. The apparatus of claim 23, wherein the host includes a central processing unit (CPU).

27. The apparatus of claim 23, wherein the host interface includes a connector having a form factor complying with at least one of Peripheral Component Interconnect Express (PCIe) specification, Serial Advanced Technology Attachment (SATA) specification, Serial Attached Small Computer System Interface (SAS) specification, Ethernet specification, and Fibre Channel specification.

28. A method comprising:

retrieving first information stored in a first memory area of a memory device;

performing an error detection operation on the first information to determine whether the first information has an error;

storing the first information in a second memory area of the memory device after the error detection operation is performed on the first information;

skipping an additional error detection operation to be performed on second information based on a result of the error detection operation performed on the first information;

retrieving second information from the first memory area; and

storing the second information in the second memory area.

29. The method claim 28, wherein the second information is stored in the second memory cells without determining whether the second information has an error if the result indicates no error is detected in the first information.

30. The apparatus of claim 28, wherein the second information is stored in the second memory cells without determining whether the second information has an error if the result indicates an error is detected in the first information, and an error value of the error is not greater than a threshold value.

31. The method of claim 28, wherein retrieving first information includes:

retrieving a first page of the first information from a block of memory cells in the first memory area, the first page including bits; and

retrieving a second page of the first information from the block of memory cells, the second page including bits.

32. The method of claim 31, wherein performing an error detection operation on the first information includes:

determining whether the first page has an error; and

determining whether the second page an error.