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Non-volatile memory including selective error correction

  • US 10,169,144 B2
  • Filed: 01/15/2016
  • Issued: 01/01/2019
  • Est. Priority Date: 01/15/2016
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a first memory area included in a memory device and a second memory area included in the memory device, the first and second memory area selectively coupled to each other through a conductive path in the memory device; and

    control circuitry included in the memory device to communicate with a memory controller, the memory controller including an error correction engine, the control circuitry of the memory device configured to retrieve first information stored in the first memory area and store the first information after the error correction engine performs an error detection operation on the first information, and to retrieve second information stored in the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information such that the error correction engine skips performing an additional error detection operation on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

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