Memory access for exactly-once messaging

• US 10,169,238 B2
• Filed: 09/30/2016
• Issued: 01/01/2019
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Katayama, Yasunao
• Primary Examiner(s): Sun, Michael
• Application Number:
  US15/281,239
• Publication Number:
  US 20180095878A1
• Time in Patent Office: 823 Days
• Field of Search: None
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A computer-implemented method is provided for enabling exactly-once messaging. The computer-implemented method includes transmitting a plurality of messages from a first location to a second location via read requests and write requests made to a memory and controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list, each slot of the lock address list associated with a lock bit. The computer-implemented method further includes initiating the read requests from the memory via the memory controller when associated lock bits are enabled and initiating the write requests from the memory via the memory controller when associated lock bits are disabled. The computer-implemented method further includes enabling and disabling the lock bits after the initiation of the write and read requests, respectively.

Claims

1. A computer-implemented method executed for enabling exactly-once messaging, the method comprising:

transmitting a plurality of messages from a first location to a second location via read requests and write requests made to a memory;

controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list, each slot of the lock address list associated with a lock bit;

initiating the read requests from the memory via the memory controller when associated lock bits are enabled;

initiating the write requests from the memory via the memory controller when associated lock bits are disabled; and

enabling and disabling the lock bits after the initiation of the write and read requests, respectively.

2. The method of claim 1, wherein the first location includes sender processes and the second location includes receiver processes.

3. The method of claim 1, wherein the memory includes a plurality of message buffers.

4. The method of claim 3, wherein the message buffers and the lock bits are segmented according to the memory controller'"'"'s access granularity to exchange variable-size messages.

5. The method of claim 4, wherein each message of the plurality of messages written in the message buffers is dispatched to a third location by detecting and, if required, copying incoming messages.

6. The method of claim 1, wherein the third location is a logical receiver, the logical receiver including a message identifier.

7. The method of claim 1, wherein memory-based protocols executed by the memory controller are supported for IO memory access architectures such as Remote Direct Memory Access (RDMA).

8. A computer-implemented method for exchanging messages between a first location and a second location via read requests and write requests made to a memory, the method comprising:

incorporating a lock address list within a memory controller for controlling the memory;

reserving portion(s) of the memory into a plurality of segmented message buffers;

assigning a lock bit and a lock address associated with the lock address list to each of the plurality of message buffers;

initiating the read requests from the message buffers when lock bits associated with the message buffers are enabled;

initiating the write requests to the message buffers when lock bits associated with the message buffers are disabled;

holding the read requests in a read queue if the lock bits associated with the message buffers are enabled;

holding the write requests in a write queue if the lock bits associated with the message buffers are disabled; and

enabling and disabling the lock bits corresponding to the write requests and the read requests after initiating the write and read requests, respectively.

9. The method of claim 8, wherein the first location includes sender processes and the second location includes receiver processes.

10. The method of claim 8, wherein each lock bit is segmented according to the memory controller'"'"'s access granularity to exchange variable-size messages.

11. The method of claim 10, wherein each message of the plurality of messages written in the message buffers is dispatched to a third location by detecting and, if required, copying incoming messages.

12. The method of claim 8, wherein the third location is a logical receiver, the logical receiver including a message identifier.

13. The method of claim 8, wherein memory-based protocols executed by the memory controller are supported for IO-based memory access architectures such as Remote Direct Memory Access (RDMA).

14. A computer system for enabling exactly-once messaging, the computer system comprising:

a memory; and

at least one processor in communication with the memory, wherein the computer system is configured to;

transmit a plurality of messages from a first location to a second location via read requests and write requests made to a memory;

control the read and write requests by a memory controller including a read queue, a write queue, and a lock address list, each slot of the lock address list associated with a lock bit;

initiate the read requests from the memory via the memory controller when associated lock bits are enabled; and

initiate the write requests from the memory via the memory controller when associated lock bits are disabled;

wherein the lock bits are enabled and disabled after the initiation of the write and read requests, respectively.

15. The computer system of claim 14, wherein the first location includes sender processes and the second location includes receiver processes.

16. The computer system of claim 14, wherein the memory includes a plurality of message buffers.

17. The computer system of claim 16, wherein the message buffers and the lock bits are segmented according to the memory controller'"'"'s access granularity to exchange variable-size messages.

18. The computer system of claim 17, wherein each message of the plurality of messages written in the message buffers is dispatched to a third location by detecting and, if required, copying incoming messages.

19. The computer system of claim 14, wherein the third location is a logical receiver, the logical receiver including a message identifier.

20. The computer system of claim 14, wherein memory-based protocols executed by the memory controller are supported for IO-based memory architectures such as Remote Direct Memory Access (RDMA).