Direct memory access descriptor

• US 10,169,271 B1
• Filed: 10/28/2014
• Issued: 01/01/2019
• Est. Priority Date: 10/28/2014
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ahmad, Sagheer, Patel, Nishit, Murray, James J.
• Primary Examiner(s): Abad, Farley
• Assistant Examiner(s): Yu, Henry W
• Application Number:
  US14/526,403
• Time in Patent Office: 1,526 Days
• Field of Search: 710308, 710 22- 23, 710 26
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Methods and systems are disclosed for transferring data using descriptors to reference memory locations at which data is to be written to or read from. Each descriptor references a respective linked list of descriptor blocks. Each of the descriptor blocks includes a contiguous portion of the memory that stores a plurality of addresses, at which data is to be written to or read from. In response to receiving the data transfer request, a set of data is transferred from a first set of addresses specified in a first descriptor to a second set of addresses specified in a second descriptor by traversing the linked lists of descriptor blocks in the first and second descriptors.

Claims

1. A system comprising:

a memory;

a first buffer;

a second buffer; and

a direct memory access circuit coupled to the memory and first and second buffers and configured to;

receive a data transfer request indicating a first descriptor and a second descriptor, wherein the first descriptor indicates a first set of addresses of the first buffer from which a set of data is to be read and the second descriptor indicates a second set of addresses of the second buffer to which the set of data is to be written;

wherein;

the first descriptor references a first linked list of descriptor blocks,

the second descriptor references a second linked list of descriptor blocks, and

each of the descriptor blocks is stored in a contiguous portion of the memory, each descriptor block stores a set of descriptor entries that references a plurality of addresses of the first or second sets of addresses, and each descriptor entry includes a marker;

in response to receiving the data transfer request, transfer the set of data from the first set of addresses in the first buffer to the second set of addresses in the second buffer by traversing the first and second linked lists of descriptor blocks;

in response to the marker in a descriptor entry of the first descriptor or the second descriptor being a pause marker, pausing the transfer of the set of data from the first set of addresses in the first buffer for a period of time until the pause marker is removed; and

in response to the marker in a descriptor entry of the first descriptor or the second descriptor being a stop marker, ending the transfer the set of data from the first set of addresses in the first buffer.

2. The system of claim 1, wherein the direct memory access circuit, in the transfer of the set of data from the first set of addresses in the first buffer, is further configured and arranged to:

select a first memory location of a first descriptor block of the first linked list as a current first memory location; and

perform a first set of operations including;

reading data from an address in the first buffer referenced by a descriptor entry at the current first memory location; and

in response to the descriptor entry at the current first memory location having a data marker indicating that the first descriptor includes additional descriptor entries;

in response to a next memory location following the current first memory location being a last memory location in a descriptor block, selecting a memory location referenced by the next memory location as a new current first memory location, and otherwise, selecting the next memory location as the new current first memory location; and

repeating the first set of operations.

3. The system of claim 2, wherein each descriptor entry in the first and second linked lists of descriptor blocks specifies an address for a respective data segment and a size of the respective data segment.

4. The system of claim 1, wherein the direct memory access circuit, in the transfer of the set of data to the second set of addresses in the second buffer, is further configured and arranged to:

select a first memory location of a first descriptor block of the second linked list as a current second memory location; and

perform a second set of operations including;

writing data to an address in the second buffer referenced by a descriptor entry at the current second memory location; and

in response to the descriptor entry at the current second memory location having a data marker indicating that the second descriptor includes additional descriptor entries;

in response to a next memory location following the current second memory location being a last memory location in a descriptor block, selecting a memory location referenced by the next memory location as a new current second memory location, and otherwise, selecting the next memory location as the new current second memory location; and

repeating the second set of operations.

5. The system of claim 1, further comprising a processing circuit coupled to the direct memory access circuit and configured to provide the data transfer request to the direct memory access circuit to initiate a transfer of the set of data from the first set of addresses in the first buffer to the second set of addresses in the second buffer.

6. The system of claim 5, wherein the processing circuit is configured to generate the first descriptor by performing a set of operations including:

for a first data segment of the set of data,

allocating a contiguous block of memory for a first descriptor block having a plurality of memory locations;

at a first one of the plurality of memory locations of the first descriptor block, storing a starting address for the first data segment in a source buffer and a size of the first data segment;

selecting a next memory location of the first plurality of memory locations following the first one of the plurality of descriptor memory locations as a current first memory location;

for each data segment of the set of data following the first data segment;

in response to the current first memory location being a last memory location of the descriptor block;

allocating an additional contiguous block of memory for an additional descriptor block having a plurality of memory locations; and

selecting a first memory location of the additional descriptor block as the current first memory location; and

storing, at the current first memory location, a starting address for the subsequent data segment and a size of the subsequent data segment.

7. The system of claim 1, wherein each descriptor block in the first linked list references no more than one other descriptor block in the first linked list.

8. The system of claim 1, wherein providing the first descriptor to the direct memory access circuit includes providing, to the direct memory access circuit, a pointer that references a first memory location of a first descriptor block of the first linked list.

9. A method for transferring a set of data from a source buffer, comprising:

providing to a direct memory access circuit, a first descriptor that indicates a set of addresses in the source buffer at which the set of data is located, wherein;

the first descriptor references a first linked list of a plurality of descriptor blocks, and

each descriptor block is stored in a contiguous portion of a memory, each descriptor block stores a plurality of descriptor entries that references a plurality of addresses of the set of addresses, and each descriptor entry includes a marker;

selecting by the direct memory access circuit, a first memory location of a first descriptor block of the first linked list as a current first location; and

performing by the direct memory access circuit a first set of operations including;

reading data from an address in the source buffer referenced by the descriptor entry at the current first location;

in response to the descriptor entry at the current first location having a data marker indicating that the first descriptor includes additional descriptor entries;

in response to the next memory location following the current first location being a last memory location in a descriptor block, selecting a memory location referenced by the next memory location as a new current first location, and otherwise, selecting the next memory location as the new current first location; and

repeating the first set of operations;

in response to the marker in the descriptor entry at the current first location being a pause marker, pausing the transfer of the set of data from the source buffer for a period of time until the pause marker is removed; and

in response to the marker in the descriptor entry at the current first location being a stop marker, ending the transfer the set of data from the source buffer.

10. The method of claim 9, further comprising:

providing to the direct memory access circuit, a second descriptor that indicates a set of addresses in a destination buffer, wherein the second descriptor references a second linked list of a plurality of descriptor blocks, each descriptor block stored in a contiguous portion of a memory that stores a plurality of descriptor entries at respective memory locations;

selecting by the direct memory access circuit, a first memory location of a first descriptor block of the second linked list as a current second memory location; and

performing by the direct memory access circuit a second set of operations including;

writing data to an address in the destination buffer referenced by the descriptor entry at the current second memory location; and

in response to the descriptor entry at the current second memory location having a data marker indicating that the second descriptor includes additional descriptor entries;

in response to the next memory location following the current second memory location being the last memory location in a descriptor block, selecting a memory location referenced by the next memory location as a new current second memory location, and otherwise, selecting the next memory location as the new current second memory location; and

repeating the second set of operations.

11. The method of claim 9, further comprising, generating the first descriptor by performing operations including:

for a first data segment of the set of data in the source buffer,

allocating a contiguous block of memory for a first descriptor block having a plurality of memory locations;

at a first one of the plurality of memory locations of the first descriptor block, storing a starting address for the first data segment and a size of the first data segment;

for each data segment of the set of data following the first data segment;

selecting a next memory location of the plurality of memory locations following the first one of the plurality of memory locations as a current third memory location;

in response to the current third memory location being the last memory location of the descriptor block;

allocating an additional contiguous block of memory for an additional descriptor block having a plurality of memory locations; and

selecting a first memory location of the additional descriptor block

as the current third memory location; and

storing, at the current third memory location, a starting address for the subsequent data segment and a size of the subsequent data segment.

12. The method of claim 9, wherein each descriptor entry in the first linked list specifies an address for a respective data segment and a size of the respective data segment.

13. The method of claim 9, wherein each descriptor block in the first linked list includes no more than one memory location belonging to another descriptor block in the first linked list.

14. The method of claim 9, wherein providing the first descriptor to the direct memory access circuit includes providing, to the direct memory access circuit, a pointer that references the first memory location of a first descriptor block of the first linked list.

15. A method for creation of a descriptor for a data transfer, comprising:

for a first data segment of a data transfer to or from a data buffer,

allocating a contiguous block of memory for a first descriptor block having a plurality of descriptor entries;

in a first one of the plurality of descriptor entries of the first descriptor block, storing a starting address for the first data segment in a source buffer and a size of the first data segment; and

selecting a next descriptor entry of the first plurality of descriptor entries following a first one of the plurality of descriptor entries as a current first descriptor entry;

for each data segment of the data transfer following the first data segment;

in response to the current first memory location being a last memory location of the descriptor block;

allocating an additional contiguous block of memory for an additional descriptor block having a plurality of descriptor entries; and

selecting a first descriptor entry of the additional descriptor block as the current first descriptor entry; and

storing, at the current first descriptor entry;

a starting address for the subsequent data segment and a size of the subsequent data segment;

adding a pause marker to a descriptor entry at the current first descriptor entry in response to the data transfer including additional data segments not ready for transfer; and

adding a stop marker to a descriptor entry at the current first descriptor entry in response to the data transfer including no additional data segments.

16. The method of claim 15, further comprising:

generating a reference pointer indicating an address of the first one of the plurality of descriptor entries of the first descriptor block.

17. The method of claim 15, further comprising:

generating a first descriptor, indicating a set of locations in the source buffer at which the set of data is located, using the method of claim 15;

generating a second descriptor, indicating a set of locations in the destination buffer, using the method of claim 15; and

providing the first and second descriptors to a direct memory access circuit.

18. The method of claim 17, further comprising:

using the direct memory access circuit, transfer data from the set of locations in the source buffer to the set of addresses in the destination buffer.