Critical path delay prediction

• US 10,169,500 B2
• Filed: 08/08/2011
• Issued: 01/01/2019
• Est. Priority Date: 08/08/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Charlebois, Margaret R., Chatty, Rashmi D., Hanudel, Christopher D., Herzl, Robert D., Milton, David W., Ogilvie, Clarence R., Szafir, Matthew P., Wilder, Tad J.
• Primary Examiner(s): Ishizuka, Yoshihisa
• Application Number:
  US13/204,812
• Publication Number:
  US 20130041608A1
• Time in Patent Office: 2,703 Days
• Field of Search: 702 79
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

Claims

1. A method of predicting a delay of one or more critical paths of an integrated circuit, the method comprising:

determining a respective delay of each of a plurality of on-board ring oscillators on the integrated circuit based on a real-time measurement of a respective frequency of each of the plurality of ring oscillators,

wherein the plurality of on-board ring oscillators includes one or more on-board high-voltage threshold (HVT) ring oscillators, one or more on-board medium-voltage threshold (SVT) ring oscillators, and one or more on-board low-voltage threshold (UVT) ring oscillators; and

calculating, using a computer system processor, a predicted delay for each of the one or more critical paths based on a delay of components of the respective critical path at a corner condition, a wire delay of the respective critical path, a delay of each of the plurality of on-board ring oscillators at a corner condition, and the determined delay of each of the plurality of on-board ring oscillators,

wherein each of the one or more critical paths include at least one HVT component on the integrated circuit having a first voltage threshold, at least one SVT component on the integrated circuit having a second voltage threshold less than the first voltage threshold, and at least one UVT component on the integrated circuit having a third voltage threshold less than both the first voltage threshold and the second voltage threshold.

2. The method of claim 1,

wherein calculating the predicted delay of each of the one or more critical paths includes calculating the predicted delay of each of the one or more critical paths according to the equation:

3. The method of claim 1, further comprising:

adding to the predicted delay of each of the one or more critical paths at least one of the following;

a timing margin or a technology margin.

4. The method of claim 1, wherein the one or more critical paths includes a plurality of critical paths and the method further comprises determining a longest predicted critical path delay from among the plurality of predicted delays calculated for the plurality of critical paths.

5. The method of claim 4, further comprising:

calculating a critical path slack according to the equation;

6. A system comprising:

at least one computing device configured for predicting a delay of one or more critical paths of an integrated circuit by performing a method comprising;

determining a respective delay of each of a plurality of on-board ring oscillators on the integrated circuit based on a real-time measurement of a respective frequency of each of the at least one plurality of ring oscillators,

wherein the plurality of on-board ring oscillators includes one or more on-board high-voltage threshold (HVT) ring oscillators, one or more on-board medium-voltage threshold (SVT) ring oscillators, and one or more on-board low-voltage threshold (UVT) ring oscillators; and

calculating a predicted delay for each of the one or more critical paths based on a delay of components of the respective critical path at a corner condition, a wire delay of the respective critical path, a delay of each of the plurality of on-board ring oscillators at a corner condition, and the determined delay of each of the plurality of on-board ring oscillators,

wherein each of the one or more critical paths include at least one HVT component on the integrated circuit having a first voltage threshold, at least one SVT component on the integrated circuit having a second voltage threshold less than the first voltage threshold, and at least one UVT component on the integrated circuit having a third voltage threshold less than both the first voltage threshold and the second voltage threshold.

7. The system of claim 6,

wherein calculating the predicted delay of each of the one or more critical paths includes calculating the predicted delay of each of the one or more critical paths according to the equation:

8. The system of claim 6, wherein the method further comprises:

adding to the predicted delay of each of the one or more critical paths at least one of the following;

a timing margin or a technology margin.

9. The system of claim 6, wherein the one or more critical paths includes a plurality of critical paths and the method further comprises determining a longest predicted critical path delay from among the plurality of predicted delays calculated for the plurality of critical paths.

10. The system of claim 9, wherein the method further comprises:

calculating a critical path slack according to the equation;

11. A system for providing a critical path delay estimate to an adaptive voltage scaling (AVS) system, wherein the AVS system reduces a power consumption of an integrated circuit, the system comprising:

at least one computing device configured to provide a critical path delay estimate for the integrated circuit by performing a method comprising;

determining a respective delay of each of a plurality of on-board ring oscillators on the integrated circuit based on a real-time measurement of a respective frequency of each of the plurality of ring oscillators,

wherein the plurality of on-board ring oscillators includes one or more on-board high-voltage threshold (HVT) ring oscillators, one or more on-board medium-voltage threshold (SVT) ring oscillators, and one or more on-board low-voltage threshold (UVT) ring oscillators; and

calculating a predicted delay for each of the one or more critical paths based on a delay of components of the respective critical path at a corner condition, a wire delay of the respective critical path, a delay of each of the plurality of on-board ring oscillators at a corner condition, and the determined delay of each of the plurality of on-board ring oscillators,

wherein each of the one or more critical paths include at least one HVT component on the integrated circuit having a first voltage threshold, at least one SVT component on the integrated circuit having a second voltage threshold less than the first voltage threshold, and at least one UVT component on the integrated circuit having a third voltage threshold less than both the first voltage threshold and the second voltage threshold;

determining the critical path delay estimate based on the predicted delay for each of the one or more critical paths; and

providing the critical path delay estimate to the AVS system.

12. The system of claim 11,

wherein calculating the predicted delay of each of the one or more critical paths includes calculating the predicted delay of each of the one or more critical paths according to the equation:

13. The system of claim 11, wherein the one or more critical paths includes a plurality of critical paths and the method further comprises determining a longest predicted critical path delay from among the plurality of predicted delays calculated for the plurality of critical paths.

14. The system of claim 13, wherein the method further comprises:

calculating a critical path slack according to the equation;

15. The system of claim 11, wherein the method further comprises:

adding a timing margin to the predicted delay of each of the one or more critical paths.

16. The system of claim 11, wherein the method further comprises:

adding a technology margin to the predicted delay of each of the one or more critical paths.

17. The system of claim 11, wherein the method further comprises:

adding a timing margin and a technology margin to the predicted delay of each of the one or more critical paths.