Achieving power supply and heat dissipation (cooling) in three-dimensional multilayer package

• US 10,169,504 B2
• Filed: 06/16/2015
• Issued: 01/01/2019
• Est. Priority Date: 05/21/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Matsumoto, Keiji
• Primary Examiner(s): Gebresilassie, Kibrom K
• Application Number:
  US14/740,906
• Publication Number:
  US 20150278417A1
• Time in Patent Office: 1,295 Days
• Field of Search: None
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 3/10 in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: H05K 7/205 : Heat-dissipating body thermally connected to heat generating element via thermal paths through printed circuit board [PCB] details of PCBs relating to heat transfer H05K1/0201
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path

Abstract

A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatus'"'"'s include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.

Claims

1. A computer-implemented method for designing a package for a stacked multiple-chip Integrated Circuit (IC) structure, the method comprising the steps of:

establishing, using the computer, a silicon (Si)-containing substrate having a wiring layer that optimizes power supply and heat dissipation for the stacked multiple-chip structure from an upper surface side of said stacked multiple-chip structure, said wiring layer supplying power to said stacked multiple-chip structure via a power supply;

setting, using the computer, a heat conductive thermal via density initial value for a chip of said stacked multiple-chip structure, wherein thermal via structures of said chip at said initial value density provide a heat dissipation route in the stacked multi-chip structure;

preparing the Si-containing substrate where said wiring layer is of a predetermined thickness and is formed on a bottom surface side of said Si-containing substrate contacting said upper surface side of said stacked multiple-chip structure and, prior to setting up an initial value of the power supply, connecting a heat dissipater a top an upper surface side of said Si-containing substrate for dissipating heat directly above the upper surface side of said Si-containing substrate;

setting, using the computer, the initial value of the power supply for said stacked multiple-chip structure supplied from said wiring layer of said Si-containing substrate;

determining, using the computer, whether the initial value of the power supply and the initial value of the thermal via density are both within a predetermined range; and

based on said determining, performing, using the computer, one or more of;

increasing or decreasing said initial value of the power supply until detecting a convergence of the initial power supply value within the predetermined range; and

increasing or decreasing said heat conductive thermal via density initial value until detecting a convergence of the thermal via density initial value within the predetermined range, and

fabricating a three-dimensional multilayer chip package including said stacked multiple-chip structure having a thermal via density corresponding to the thermal via density value at the detected convergence, said three-dimensional multilayer chip package for receiving a power supply input at a value corresponding to the power supply value at the detected convergence.

2. The method of claim 1, wherein the initial value for said thickness of said wiring layer is between 10 μ

m and 15 μ

m.

3. The method of claim 1, further comprising:

designing, using the computer, the apparatus to further include;

an organic substrate having a concave part, the stacked multiple-chip structure being arranged so that said stacked multiple-chip structure is situated in the concave part of said organic substrate to house the stacked multiple-chip structure.

4. The method of claim 3, further comprising:

designing, using the computer, the apparatus to further include;

an interposer for installing said stacked multiple-chip structure within said concave part of said organic substrate, a bottom surface of said stacked multiple-chip structure for placement on said interposer.