High speed processing of financial information using FPGA devices

• US 10,169,814 B2
• Filed: 07/01/2013
• Issued: 01/01/2019
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Ip Reservoir, LLC
• Inventors: Parsons, Scott, Taylor, David E., Schuehler, David Vincent, Franklin, Mark A., Chamberlain, Roger D.
• Primary Examiner(s): Borlinghaus, Jason
• Application Number:
  US13/932,274
• Publication Number:
  US 20130290163A1
• Time in Patent Office: 2,010 Days
• Field of Search: None
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

A high speed apparatus and method for processing financial instrument order books are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to synthesize quote events associated with a plurality of financial instruments from a financial market data feed.

Claims

1. A method comprising:

a ticker plant maintaining a plurality of financial instrument order books in a memory, each financial instrument order book corresponding to a financial instrument and comprising data representative of a plurality of bids and offers for the corresponding financial instrument, the data comprising a price field for the bids and offers, wherein the ticker plant includes a reconfigurable logic device and a processor in cooperation with the reconfigurable logic device, wherein the reconfigurable logic device includes firmware logic deployed thereon;

the processor executing an operating system that includes a user space for a user mode and a kernel space for a kernel mode, wherein the executing step comprises;

the processor receiving a financial market data feed through a network protocol stack, wherein the financial market data feed comprises a plurality of streaming financial market data order messages from an exchange, and wherein the streaming messages within the feed comprise financial market data that represent a plurality of offers to buy and sell a plurality of financial instruments;

the processor normalizing the financial market data;

the processor using shared memory that is mapped into the kernel space and the user space to store the normalized financial market data; and

the processor facilitating DMA transfers of the normalized financial market data from the shared memory to the reconfigurable logic device;

the reconfigurable logic device receiving financial market data from the shared memory via the DMA transfers;

the firmware logic updating the financial instrument order books based on the received financial market data;

the firmware logic detecting that a generated update for a financial instrument order book causes a best bid or offer price for the financial instrument corresponding to that financial instrument order book to change to a new value; and

in response to the detecting, the firmware logic synthesizing a quote for that financial instrument, the synthesized quote comprising the new value for that financial instrument'"'"'s best bid or offer price.

2. The method of claim 1 wherein the feed comprises a plurality of streaming financial market data messages other than a quote stream, the method further comprising:

providing the synthesized financial instrument quote to a trading application.

6. The method of claim 1 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA), and wherein the firmware logic is resident on the FPGA.

7. The method of claim 1 wherein the shared memory comprises first shared memory that is mapped into the kernel space and the user space and second shared memory that is mapped into the kernel space and the user space, and wherein the executing step further comprises:

a first driver executing within the kernel space of the operating system while the operating system is in the kernel mode, wherein the first driver executing step comprises the first driver (1) maintaining a kernel level interface into the network protocol stack and (2) copying the streaming financial market data from the network protocol stack into the first shared memory without a transition to the user mode; and

user mode code executing within the user space of the operating system, wherein the user mode code executing step comprises the user mode code (1) accessing financial market data from the first shared memory, (2) normalizing the accessed financial market data, and (3) writing the normalized financial market data to the second shared memory.

8. The method of claim 7 wherein the processor executing step further comprises:

a second driver executing within the kernel space of the operating system while the operating system is in the kernel mode, the second driver executing step comprising the second driver facilitating the DMA transfers of the normalized financial market data from the second shared memory to the reconfigurable logic device.

9. The method of claim 8 wherein the user mode code comprises a plurality of threads, each thread normalizing a different group of the accessed financial market data independently of the other threads.

10. The method of claim 1 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

11. The method of claim 1 wherein the shared memory comprises a ring buffer.

3. An apparatus comprising:

a ticker plant, the ticker plant comprising a memory, a processor, and a reconfigurable logic device, the reconfigurable logic device having firmware logic deployed thereon;

wherein the ticker plant is configured to maintain a plurality of financial instrument order books in the memory, each financial instrument order book corresponding to a financial instrument and comprising data representative of a plurality of bids and offers for the corresponding financial instrument, the data comprising a price field for the bids and offer;

wherein the processor is configured to (1) execute an operating system that includes a user space for a user mode and a kernel space for a kernel mode, (2) receive a financial market data feed through a network protocol stack, wherein the financial market data feed comprises a plurality of streaming financial market data order messages from an exchange, and wherein the streaming messages within the feed comprise financial market data that represent a plurality of offers to buy and sell a plurality of financial instruments, (3) normalize the financial market data, (4) use shared memory that is mapped into the kernel space and the user space to store the normalized financial market data, and (5) facilitate DMA transfers of the normalized financial market data from the shared memory to the reconfigurable logic device;

wherein the reconfigurable logic device is configured to receive financial market data from the shared memory via the DMA transfers; and

wherein the firmware logic is configured to (1) process the normalized financial market data, (2) generate updates to the financial instrument order books based on the processing operation, (3) detect that a generated update for a financial instrument order book causes a best bid or offer price for the financial instrument corresponding to that financial instrument order book to change to a new value, (4) in response to the detection, synthesize a quote for that financial instrument, the synthesized quote comprising the new value for that financial instrument'"'"'s best bid or offer price.

4. The apparatus of claim 3 wherein the feed comprises a plurality of streaming financial market data messages other than a quote stream, and wherein the reconfigurable logic device is further configured to provide the synthesized financial instrument quote to a trading application.

5. The apparatus of claim 3 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA), and wherein the firmware logic is resident on the FPGA.

12. The apparatus of claim 3 wherein the shared memory comprises first shared memory that is mapped into the kernel space and the user space and second shared memory that is mapped into the kernel space and the user space;

wherein a first driver that executes within the kernel space of the operating system while the operating system is in the kernel mode is configured to (1) maintain a kernel level interface into the network protocol stack and (2) copy the streaming financial market data from the network protocol stack into the first shared memory without a transition to the user mode; and

wherein user mode code that executes within the user space of the operating system is configured to (1) access financial market data from the first shared memory, (2) normalize the accessed financial market data, and (3) write the normalized financial market data to the second shared memory.

13. The apparatus of claim 12 wherein a second driver that executes within the kernel space of the operating system while the operating system is in the kernel mode is configured to facilitate the DMA transfers of the normalized financial market data from the second shared memory to the reconfigurable logic device.

14. The apparatus of claim 13 wherein the user mode code comprises a plurality of threads, each thread configured for execution to normalize a different group of the accessed financial market data independently of the other threads.

15. The apparatus of claim 3 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

16. The apparatus of claim 3 wherein the shared memory comprises a ring buffer.