Display device and method of driving the same

• US 10,170,049 B2
• Filed: 09/23/2016
• Issued: 01/01/2019
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ryu, Sungbin, Lee, Youngjang
• Primary Examiner(s): Siddiqui, Md Saiful A
• Application Number:
  US15/274,003
• Publication Number:
  US 20170092198A1
• Time in Patent Office: 830 Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes

Abstract

Provided are a display device and method of driving the same. A display device includes: a display panel including: intersecting data lines and gate lines, and pixels in a matrix, a timing controller allowing the pixels to be driven at a lower refresh rate in low-speed driving mode than in normal driving mode, and controlling a horizontal blank time to be longer in the low-speed driving mode than the normal driving mode, the horizontal blank time being a period of time during which no data voltage exists, between an n^th data voltage and an (n+1)^th data voltage consecutively supplied through the data lines, “n” being a positive integer, and a display panel driving circuit writing one frame of image data to the pixels during one frame period in the normal driving mode, and in a distributed manner during a second to fourth frame period in the low-speed driving mode.

Claims

1. A display device, comprising:

a display panel comprising;

data lines and gate lines intersecting each other; and

pixels in a matrix;

a timing controller configured to;

allow the pixels to be driven at a lower refresh rate in low-speed driving mode than in normal driving mode; and

control a horizontal blank time to be longer in the low-speed driving mode than in the normal driving mode, the horizontal blank time being a period of time during which no data voltage exists, between an n^th data voltage, supplied to the pixels on an nth horizontal line of the display panel, and an (n+1)^th data voltage, supplied to the pixels on an (n+1)^th horizontal line of the display panel, that are consecutively supplied through the data lines, where “

n”

is a positive integer greater than or equal to 1; and

a display panel driving circuit configured to;

write data to the display panel;

write one frame of image data to the pixels during one frame period in the normal driving mode; and

write one frame of image data to the pixels in a distributed manner during an i-frame period in the low-speed driving mode, where “

i”

is a positive integer from 2 to 4,

wherein the horizontal blank time is extended so that a next data voltage is supplied to the data lines after discharging the parasitic capacitance of the data lines in the low-speed driving mode.

2. The display device of claim 1, wherein, in the low-speed driving mode, each pixel:

charges itself with a data voltage once in the i-frame period; and

holds the data voltage during a unit of time set for the low-speed driving mode, except for the i-frame period.

3. The display device of claim 1, wherein the pixels are driven by progressive scanning or interlaced scanning in the normal driving mode and low-speed driving mode.

4. The display device of claim 1, wherein the pixels are driven by:

progressive scanning in the normal driving mode; and

interlaced scanning in the low-speed driving mode.

5. The display device of claim 1, wherein the pixels are driven by:

interlaced scanning in the normal driving mode; and

progressive scanning in the low-speed driving mode.

6. The display device of claim 1, wherein the timing controller controls the horizontal blank time in the low-speed driving mode to be two times or more longer than the horizontal blank time in the normal driving mode.

7. The display device of claim 1, wherein the pixels comprise oxide transistors.

8. The display device of claim 1, wherein the pixels comprise:

oxide transistors; and

polycrystalline transistors.

9. The display device of claim 1, wherein the pixels are driven by progressive scanning or interlaced scanning in the normal driving mode and the low-speed driving mode.

10. A method of driving a display device comprising a display panel, comprising data lines and gate lines intersecting each other and pixels in a matrix, and a display panel driving circuit for writing data to the display panel, the method comprising:

reducing the driving frequency and power consumption of the display panel driving circuit in low-speed driving mode compared to normal driving mode;

controlling a horizontal blank time to be longer in the low-speed driving mode than in the normal driving mode, the horizontal blank time being a period of time during which no data voltage exists, between an n^th data voltage, supplied to the pixels on an nth horizontal line of the display panel, and an (n+1)^th data voltage, supplied to the pixels on an (n+1)^th horizontal line of the display panel, that are consecutively supplied through the data lines, where “

n”

is a positive integer greater than or equal to 1, the horizontal blank time being extended so that a next data voltage is supplied to the data lines after discharging the parasitic capacitance of the data lines in the low-speed driving mode;

writing, by the display panel driving circuit, one frame of image data to the pixels during one frame period in the normal driving mode; and

writing, by the display panel driving circuit, one frame of image data to the pixels in a distributed manner during an i-frame period in the low-speed driving mode, where “

i”

is a positive integer from 2 to 4.

11. The method of claim 10, further comprising, in the low-speed driving mode, each pixel:

charging itself with a data voltage once in the i-frame period; and

holding the data voltage during a unit of time set for the low-speed driving mode, except for the i-frame period.

12. The method of claim 10, wherein the pixels are driven by progressive scanning or interlaced scanning in the normal driving mode and low-speed driving mode.

13. The method of claim 10, wherein the pixels are driven by:

progressive scanning in the normal driving mode; and

interlaced scanning in the low-speed driving mode.

14. The method of claim 10, wherein the pixels are driven by:

interlaced scanning in the normal driving mode; and

progressive scanning in the low-speed driving mode.

15. The method of claim 10, wherein the timing controller controls the horizontal blank time in the low-speed driving mode to be two times or more longer than the horizontal blank time in the normal driving mode.

16. A display device, comprising:

a display panel comprising;

a plurality of data lines and gate lines intersecting each other; and

a plurality of pixels in a matrix;

a timing controller configured to;

allow the pixels to be driven at a lower refresh rate in a low-speed driving mode than in a normal driving mode; and

control a horizontal blank time to be longer in the low-speed driving mode than in the normal driving mode, the horizontal blank time being a period of time during which no data voltage exists, between an n^th data voltage, supplied to the pixels on an nth horizontal line of the display panel, and an (n+1)^th data voltage, supplied to the pixels on an (n+1)^th horizontal line of the display panel, that are consecutively supplied through the data lines, where “

n”

is a positive integer greater than or equal to 1; and

a display panel driving circuit configured to write data to the display panel;

wherein the horizontal blank time is longer in the low-speed driving mode than in the normal driving mode to ensure enough time to discharge a parasitic capacitance, thereby minimizing a pixel voltage variation by residual charge in the parasitic capacitance connected to the data lines.

17. The display device of claim 16, wherein:

less than one frame of data is written to some pixels during one frame period; and

a remaining data is written to some other pixels in the low-speed driving mode.

18. The display device of claim 16, wherein the display panel driving circuit is configured to write one frame of image data to the pixels in a distributed manner during an i-frame period in the low-speed driving mode, where “

i”

is a positive integer from 2 to 4.

19. The display device of claim 16, wherein the horizontal blank time in the low-speed driving mode is two times or more longer than the horizontal blank time in the normal driving mode.

20. The display device of claim 16, wherein the pixels comprise:

oxide transistors; and

polycrystalline transistors.