Apparatuses and methods involving accessing distributed sub-blocks of memory cells

• US 10,170,169 B2
• Filed: 09/29/2017
• Issued: 01/01/2019
• Est. Priority Date: 08/21/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/720,960
• Publication Number:
  US 20180122443A1
• Time in Patent Office: 459 Days
• Field of Search: 36518511
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

Claims

1. A method, comprising:

accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time, wherein the first and second sub-blocks of memory cells are part of a first block of memory cells of multiple blocks of memory cells of a memory array,

wherein the first and second sub-blocks within the block are enabled to be accessed simultaneously, and wherein the memory cells in a second block of memory cells are not enabled to be accessed when memory cells of the first block are being accessed; and

wherein the first sub-block of the block of memory cells and the second sub-block of the block of memory cells are not in the same row or the same column of the block of memory cells.

2. The method of claim 1, wherein accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time comprises accessing the first sub-block having a first coordinate and a second coordinate at the same time as accessing the second sub-block having a first coordinate and a second coordinate, wherein the first and second coordinates of the first sub-block are not the same as the first and second coordinates of the second sub-block.

3. The method of claim 1, wherein accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time comprises accessing the first sub-block according to an x-coordinate and a y-coordinate that are not the same as an x-coordinate and a y-coordinate of the second sub-block, where the x- and y-coordinates are part of a Cartesian coordinate system.

4. The method of claim 1, wherein accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time comprises accessing the first sub-block using a radial coordinate and an angular coordinate that are not the same as a radial coordinate and an angular coordinate of the second sub-block.

5. The method of claim 1, further comprising simultaneously accessing additional sub-blocks of the first block of memory cells with the first and second sub-blocks, wherein none of the multiple simultaneously accessed sub-blocks is in a same row or column of the first block of memory cells as another simultaneously accessed sub-block.

6. The method of claim 5, wherein the multiple accessed sub-blocks of memory cells are in a two-dimensional array of memory cells.

7. The method of claim 5, wherein the multiple accessed sub-blocks of memory cells are in a three-dimensional array of memory cells.

8. A method comprising:

receiving a memory request in an apparatus; and

executing the memory request in the apparatus, wherein the executing comprises;

enabling multiple sub-blocks in a block of memory cells to be accessed simultaneously in response to the memory request, while leaving other sub-blocks in the block of memory cells disabled for access;

wherein the memory array comprises rows and columns of sub-blocks of memory cells, and

wherein the enabled sub-blocks are each in a row and column that does not include another enabled sub-block;

accessing first data in a first sub-block of memory cells of the block of memory cells; and

accessing second data in a second sub-block of memory cells of the block of memory cells simultaneously with accessing the first data.

9. The method of claim 8, wherein accessing the first data comprises writing the first data to memory cells of the first sub-block and wherein accessing the second data comprises writing the second data to memory cells of the second sub-block.

10. The method of claim 8, wherein accessing the first data comprises reading the first data from memory cells of the first sub-block and wherein accessing the second data comprises reading the second data from memory cells of the second sub-block.

11. The method of claim 8, wherein accessing the first data comprises erasing the first data from memory cells of the first sub-block and wherein accessing the second data comprises erasing the second data from memory cells of the second sub-block.

12. The method of claim 8, wherein executing the memory request further comprises accessing third data in a third sub-block of the memory block at the same time that the first data and the second data are being accessed, wherein the third sub-block is in a different row of sub-blocks and a different column of sub-blocks than both the first sub-block and the second sub-block of the memory block.

13. The method of claim 8, wherein enabling multiple sub-blocks comprises providing an enable signal for each enabled sub-block in response to decoding signals in a decoder circuit.

14. The method of claim 13, further comprising changing the decoding signals to disable sub-blocks that were enabled and to enable sub-blocks that were not enabled.

15. The method of claim 8, wherein enabling multiple sub-blocks further comprises enabling access lines coupled to the memory cells in the sub-blocks to receive one of programming voltages, read voltages, and erase voltages.

16. A 3D memory device comprising:

in a stack an array multiple arrays of memory cells, each of the stacked arrays having multiple sub-blocks of memory cells, accessing multiple sub-blocks of memory cells in each of multiple arrays simultaneously;

wherein the simultaneously accessed sub-blocks in a first array are in different rows and columns from one another; and

wherein the simultaneously accessed sub-blocks in a second array are in different rows and columns from one another.

17. The 3D memory device of claim 16, wherein the simultaneously accessed sub-blocks in the first array are each in corresponding positions in the rows and columns in the first array to the positions in the rows and columns of each of the simultaneously accessed sub-blocks in the second array.

18. The 3D memory device of claim 16, wherein the simultaneously accessed sub-blocks in the first array are each in different positions in rows and columns in the first array than the positions in rows and columns of the simultaneously accessed sub-blocks in the second array.

19. The 3D memory device of claim 16, wherein the simultaneously accessed sub-blocks in the first array are vertically aligned with corresponding simultaneously accessed sub-blocks of the second array.

20. The 3D memory device of claim 16, wherein the stack of multiple arrays of memory cells includes multiple blocks of memory cells, wherein one or more blocks of memory cells includes sub-blocks in each of multiple stacked arrays.

21. The 3D memory device of claim 20, wherein the simultaneously accessed sub-blocks in the first array and the simultaneously accessed sub-blocks in the second array are part of a single block.

22. The 3D memory device of claim 20, wherein all memory cells in a block of memory cells are enabled to be accessed simultaneously, and the memory cells in a second block of memory cells are not enabled to be accessed when memory cells of the first block of memory cells are being accessed.