Apparatus and methods including source gates

• US 10,170,189 B2
• Filed: 09/29/2017
• Issued: 01/01/2019
• Est. Priority Date: 08/15/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Ahmed, Shafqat, Hasnat, Khaled, Parat, Krishna K.
• Primary Examiner(s): Yoha, Connie
• Application Number:
  US15/721,007
• Publication Number:
  US 20180122481A1
• Time in Patent Office: 459 Days
• Field of Search: 36518511, 36518523, 36523006
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Claims

1. A memory array, comprising:

multiple strings of charge storage devices, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns, each of the multiple strings coupled to a common source through both a source gate device and a source select gate device;

wherein each source gate device includes a gate, and is configured to partially control conduction between the pillar of the respective string and the common source, wherein each source select gate device includes a gate and is also configured to partially control conduction between the pillar of the respective string and the common source,

wherein the gates of the source gate devices associated with each of the multiple strings of charge storage devices are coupled together to be controlled in common; and

wherein the gates of source select gate devices associated with a first group of strings of the multiple strings of charge storage devices are coupled together to be controlled in common, wherein the first group of strings is less than all of the multiple strings of charge storage devices.

2. The memory array of claim 1, further comprising multiple drain select gate devices,

each drain select gate associated with a respective string of the multiple strings of charge storage devices,

each drain select gate device having a gate, and

wherein the gates of the drain select gate devices associated with the first group of strings are coupled to one another to be controlled in common.

3. The memory array of claim 1, wherein each source gate device at least partially surrounds the pillar of the string of charge storage devices with which the source gate device is associated.

4. The memory array of claim 1, wherein each source select gate device at least partially surrounds the pillar of the string of charge storage devices with which the source select gate device is associated.

5. The memory array of claim 1, wherein each source select gate device is between the plurality of string of charge storage devices associated with a respective pillar and the source gate device associated with such respective pillar.

6. The memory array of claim 1, wherein the multiple strings of charge storage devices comprises all strings of charge storage devices in a block of memory.

7. The memory array of claim 1, wherein the first group of strings of charge storage devices comprises the strings in a sub-block of the memory array.

8. The memory array of claim 1, wherein the first group of strings of charge storage devices comprises only strings in a single column of the memory array.

9. The memory array of claim 8, wherein the first group of strings of charge storage devices comprises all strings in a single column of the memory array of the memory array.

10. A memory device, comprising:

multiple strings of charge storage devices in a block of memory, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns in the block of memory;

multiple drain select gate devices, each drain select gate device at least partially surrounding a respective pillar of one of the multiple strings of charge storage devices,

wherein the drain select gate device is between the string of charge storage devices associated with the pillar and a respective data line, and

wherein the gates of drain select gate devices associated with a first group of strings are coupled to one another to be controlled in common;

multiple source gate devices, each source gate at least partially surrounding a respective pillar of one of the multiple strings, each source gate device coupled to a source and configured to partially control conduction between the pillar and the source,

wherein each source gate device includes a gate,

wherein the gate of each source gate device is coupled to the gates of multiple additional source gate devices associated with a second group of strings of charge storage devices, wherein the first group of strings is a subset of the second group of strings; and

wherein the second group of strings includes a source gate device of a string in the same row, and further includes the gate of a source gate device in another row, to be controlled in common; and

multiple source select gate devices, each source select gate device at least partially surrounding a respective pillar of one of the multiple strings,

wherein each source select gate device is between the plurality of string of charge storage devices associated with the pillar and the source gate device, and is configured to partially control conduction between the pillar and the source, and

wherein the source select gate devices associated with the first group of strings are coupled to one another to be controlled in common.

11. The memory device of claim 10, wherein the second group of strings comprises all strings in the block of memory.

12. The memory device of claim 10, wherein the first group of strings of charge storage devices comprises the strings in a sub-block of the memory array.

13. The memory device of claim 10, wherein the first group of strings comprises strings in a single column in the block of memory.

14. The memory device of claim 13, wherein the first group of strings comprises all strings in a single column in the block of memory.

15. The memory device of claim 10, wherein each string of charge storage devices extends vertically, with each charge storage device in a string formed in a respective tier of multiple vertically arranged tiers, and wherein each charge storage device includes a gate;

and

wherein each tier comprises a respective access line, wherein each access line is coupled to gates of multiple charge storage devices in the respective tier, including a single charge storage device gate from each of multiple memory cell strings.

16. A method for operating a memory array, wherein the memory array comprises:

multiple strings of charge storage devices, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns, each of the multiple strings coupled to a common source through both of a source gate device and a source select gate device;

wherein each source gate device includes a gate, and is configured to partially control conduction between the pillar of the respective string and the common source,

wherein each source select gate device includes a gate and is configured to partially control conduction between the pillar of the respective string and the common source,

wherein the gates of the source gate devices associated with each of the multiple strings of charge storage devices are coupled together to be controlled in common,

wherein the gates of source select gate devices associated with a first group of strings of the multiple strings of charge storage devices are coupled together to be controlled in common,

wherein the first group of strings is less than all of the multiple strings of charge storage devices; and

wherein the multiple charge storage devices each includes a respective gate, and

wherein the gates of individual respective charge storage devices, one from each string of a second group of strings of the multiple strings of charge storage devices, are coupled to a respective access line to be controlled in common;

the method comprising;

biasing the common source to a first voltage;

controlling a first source select device to an “

on”

state, the first source select gate device associated with a selected string of charge storage devices, while controlling multiple source select gate devices associated with unselected strings of charge storage devices to an “

off”

state;

controlling the source gate devices associated with both the selected string of charge storage devices and the unselected strings of charge storage devices to an “

on”

state;

biasing, with the read voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices; and

biasing multiple unselected access lines with a voltage greater than the read voltage, the unselected access lines coupled to multiple charge storage devices other than the selected charge storage device.

17. The method of claim 16, wherein each string of charge storage devices extends vertically, with each charge storage device in a string formed in a respective tier of multiple vertically arranged tiers, and wherein each charge storage device includes a gate;

wherein each tier comprises a respective access line, wherein each access line is coupled to gates of multiple charge storage devices in the respective tier, including a single charge storage device gate from each of multiple memory cell strings.

18. The method of claim 16, wherein the memory array further comprises multiple drain select gate devices, each drain select gate associated with a respective string of the multiple strings of charge storage devices, each drain select gate device having a gate, and wherein the gates of the drain select gate devices associated with the first group of strings are coupled to one another to be controlled in common;

and

wherein the method further comprises;

controlling to an “

on”

state a selected drain select gate associated with the selected string of charge storage devices; and

controlling multiple unselected drain select gates to an “

off”

state, the unselected drain select gates associated with strings of charge storage devices other than the selected string.

19. A method for operating a memory array having multiple strings of charge storage devices arranged in rows and columns, comprising:

biasing a common source to the multiple strings to a first voltage;

controlling a first source select device associated with a selected string of memory cells to an “

on”

state, while controlling multiple additional source select gate devices associated with respective unselected strings of charge storage devices to an “

off”

state;

controlling source gate devices associated with both the selected string of charge storage devices and the unselected strings of charge storage devices to an “

on”

state, wherein a respective source select device and source gate device are connected in series with one another between the common source and a respective string of charge storage devices and are controllable independently of one another;

biasing, with the read voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage device, wherein the selected access line is coupled to the selected charge storage device and also to charge storage devices in unselected strings of charge storage devices; and

biasing multiple unselected access lines with a voltage greater than the read voltage, the unselected access lines coupled to multiple charge storage devices other than the selected charge storage device.

20. The method of claim 19, further comprising:

controlling to an “

on”

state a drain select device associated with the selected string of charge storage devices, or in a drain select device of each string is located on the opposite side of the charge storage devices from the respective source gate device and source select device of the string; and

controlling multiple drain select gates associated with strings of charge storage devices other than the selected string to an “

off”

state.

21. The method of claim 19, wherein each string of charge storage devices extends vertically and is associated with a respective conductive pillar, and wherein at least a portion of the respective source gate device and source select device of each string extends at least partially around the respective pillar of the string of charge storage devices.