Low temperature fabrication of lateral thin film varistor

• US 10,170,224 B2
• Filed: 11/22/2017
• Issued: 01/01/2019
• Est. Priority Date: 02/26/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Graf, Richard S., Mandal, Sudeep
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/821,433
• Publication Number:
  US 20180096760A1
• Time in Patent Office: 405 Days
• Field of Search: None
• CPC Class Codes: H01C 17/006 adapted for manufacturing resistor chips
• CPC Class Codes: H01C 17/06553 composed of a combination of metals and oxides
• CPC Class Codes: H01C 17/12 by sputtering
• CPC Class Codes: H01C 17/245 by mechanical means, e.g. sand blasting, cutting, ultrasonic treatment
• CPC Class Codes: H01C 17/288 by thin film techniques
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01C 7/1013 Thin film varistors
• CPC Class Codes: H01C 7/108 Metal oxide
• CPC Class Codes: H01C 7/112 ZnO type
• CPC Class Codes: H01C 7/12 Overvoltage protection resistors series resistors structurally associated with spark gaps H01T1/16
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 28/24 : with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Claims

1. A lateral thin film varistor device, comprising:

a substrate;

a dielectric layer on the substrate;

two electrodes on the dielectric layer and spaced apart from each other in a first, lateral direction; and

a continuous, varistor layer on the dielectric layer and located between, and in contact with, the two electrodes, and comprising regions of a first metal oxide layer, and regions of a second metal oxide layer, and wherein;

the regions of the first metal oxide layer alternate with the regions of the second metal oxide layer in the lateral direction between the two electrodes,

the regions of the second metal oxide layer project outside the regions of the first metal oxide layer in a second, transverse direction perpendicular to the lateral direction, and

two of the regions of the first metal oxide layer are located laterally outside the regions of the second metal oxide layer, in contact with the two electrodes.

2. The lateral thin film varistor device according to claim 1, further comprising first and second conductive vias, each of the conductive vias being connected to a respective one of the electrodes.

3. The lateral thin film varistor device according to claim 2, wherein the conductive vias are laterally outside of the continuous varistor layer.

4. The lateral thin film varistor device according to claim 1, wherein the regions of the first metal oxide layer and the regions of the second metal oxide layer have substantially co-planar upper surfaces.

5. A lateral thin film varistor device according to claim 4, wherein the two electrodes have upper surfaces substantially coplanar with the upper surfaces of the regions of the first and second meal oxide layers.

6. A lateral thin film varistor device according to claim 1, wherein the first metal oxide layer is comprised of zinc oxide.

7. A lateral thin film varistor device according to claim 6, wherein the second metal oxide layer is comprised of bismuth oxide.

8. A lateral thin film varistor device according to claim 7, wherein the first metal oxide layer is doped with aluminum oxide, and the second metal oxide layer is doped with aluminum oxide.

9. A lateral thin film varistor device according to claim 1, wherein the regions of the first metal oxide layer have a thickness between 50 nm and 500 nm.

10. A lateral thin film varistor device according to claim 9, wherein the first metal oxide layer includes zinc crystal grains having a size between 10 nm and 300 nm.

11. A method of forming a lateral thin film varistor device, comprising:

forming a dielectric layer on a substrate;

forming a continuous, varistor layer on the dielectric layer, including

forming regions of a first metal oxide layer on the dielectric using a first sputtering process and a first annealing process,

forming regions of a second metal oxide layer on the dielectric using a second sputtering process and a second annealing process,

alternating the regions of the first metal oxide layer with the regions of the second metal oxide layer in a first, lateral direction,

projecting the regions of the second metal oxide layer outside the regions of the first metal oxide layer in a second, transverse direction perpendicular to the lateral direction, and

locating two of the regions of the first metal layer laterally outside the regions of the second metal oxide layer; and

forming two electrodes on the dielectric layer spaced apart and outside of the continuous, varistor layer, in the lateral direction, with said two regions of the first metal layer in contact with the two electrodes.

12. The method according to claim 11, further comprising connecting a first conductive via to a first of the electrodes, and connecting a second conductive vias to a second of the electrodes.

13. The method according to claim 12, wherein the conductive vias are laterally outside of the continuous, varistor layer.

14. The method according to claim 11, wherein the regions of the first metal oxide layer and the regions of the second metal oxide layer have substantially co-planar upper surfaces.

15. The method according to claim 14, wherein the forming two electrodes on the dielectric layer includes forming upper surfaces of the two electrodes substantially co-planar with the upper surfaces of the regions of the first and second metal oxide layers.

16. A method of forming a lateral thin film varistor device, comprising:

forming a dielectric layer on a substrate;

forming a continuous, varistor layer on the dielectric layer, including

forming regions of a zinc oxide layer on the dielectric using a first sputtering process and a first annealing process,

forming regions of a bismuth oxide layer on the dielectric using a second sputtering process and a second annealing process,

alternating the regions of the zinc oxide layer with the regions of the bismuth oxide layer in a first, lateral direction,

projecting the regions of the bismuth oxide layer outside the regions of the zinc oxide layer in a second, transverse direction perpendicular to the lateral direction, and

locating two of the regions of the zinc oxide layer laterally outside the regions of the bismuth oxide layer; and

forming two electrodes on the dielectric layer spaced apart and outside of, and in contact with, the continuous, varistor layer, in the lateral direction.

17. The method according to claim 16, further comprising:

doping the zinc oxide layer with aluminum oxide; and

doping the bismuth oxide layer with aluminum oxide.

18. The method according to claim 16, wherein the regions of the zinc oxide layer have a thickness between 50 nm and 500 nm.

19. The method according to claim 18, wherein the zinc metal oxide layer includes zinc crystal grains having a size between 10 nm and 300 nm.

20. The method according to claim 16, wherein the forming two electrodes on the dielectric layer includes forming the two electrodes outside of, and in contact with, the two regions of the zinc oxide layer.