Self-aligned nanotube structures

• US 10,170,304 B1
• Filed: 10/25/2017
• Issued: 01/01/2019
• Est. Priority Date: 10/25/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kwon, Oh-Jung, Ortolland, Claude, Schepis, Dominic, Collins, Christopher
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US15/793,621
• Time in Patent Office: 433 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02606 Nanotubes carbon nanotubes H10K85/211
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/491 : Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 85/20 : Carbon compounds, e.g. carbon nanotubes or fullerenes

Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The structure includes at least one nanotube structure supported by a plurality of spacers and an insulator material between the spacers and contacting the at least one nanotube structure.

Claims

1. A structure, comprising at least one nanotube structure between adjacent fin structures and supported by a plurality of spacers, and an insulator material between the spacers which contacts the spacers at a bottom surface thereof, the spacers and the insulator material lining the adjacent fin structures.

2. The structure of claim 1, further comprising a gate material formed around the insulator material, wherein the insulator material is a gate dielectric material which surrounds the at least one nanotube structure.

3. The structure of claim 1, wherein the at least one nanotube structure is composed of another insulator material and a fill material.

4. The structure of claim 3, wherein the fill material is a group III or group V material.

5. The structure of claim 3, wherein the fill material is graphene.

6. The structure of claim 3, wherein the fill material is a silicon based material.

7. The structure of claim 3, wherein the insulator material lines the adjacent fin structures and exposed portions of the substrate material.

8. The structure of claim 3, further comprising epitaxial source and drain regions adjacent to respective spacers and in contact with end portions of the at least one nanotube structure.

9. The structure of claim 8, further comprising a gate-all-around FET which comprises a gate material surrounding the at least one nanotube structure between the spacers.

10. The structure of claim 9, wherein the epitaxial source and drain regions are directly on sides of the spacers.

11. The structure of claim 10, wherein the gate material supports the at least one nanotube structure.

12. The structure of claim 11, wherein the gate material is in direct contact with the at least one nanotube structure.

13. The structure of claim 12, further comprising a cavity in which the at least one nanotube structure is formed therein.

14. The structure of claim 13, wherein the cavity is lined with the insulator material.

15. The structure of claim 14, wherein the cavity is filled with the fill material.

16. A structure, comprising:

a plurality of fin structures;

an aligned nanotube structure between adjacent fin structures of the plurality of fin structures;

spacers supporting the aligned nanotube structure between the adjacent fin structures;

a material lining the plurality of fin structures which is between and in contact with the spacers between the adjacent fin structures; and

epitaxial source and drain regions adjacent to the spacers and directly on sides of the spacers.

17. The structure of claim 16, wherein the aligned nanotube structure includes a fill material.

18. The structure of claim 17, wherein the fill material is one of graphene, a heterogeneous material and a silicon material.

19. The structure of claim 16, further comprising a gate material surrounding the material and the aligned nanotube structure to form an all-around gate structure, the material being a gate dielectric material.

20. The structure of claim 16, wherein the aligned nanotube structure has a circular cross-sectional shape.