Semiconductor device and method of manufacturing the semiconductor device

• US 10,170,363 B2
• Filed: 07/17/2017
• Issued: 01/01/2019
• Est. Priority Date: 12/20/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Jong Su
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US15/651,117
• Publication Number:
  US 20180174905A1
• Time in Patent Office: 533 Days
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53204 Conductive materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure

Abstract

An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.

Claims

1. An interconnection structure of a semiconductor integrated circuit device comprising:

a first conductive pattern having a first width and a first length;

a second conductive pattern arranged over the first conductive pattern, the second conductive pattern having a second width and a second length being different from the first length;

a dielectric layer interposed between the first conductive pattern and the second conductive pattern; and

a contact part configured to simultaneously make contact with the first conductive pattern and the second conductive pattern,

wherein the second conductive pattern is configured to expose an edge portion of the first conductive pattern, and the contact part is configured to make contact with the an edge portion of the second conductive pattern and the exposed edge portion of the first conductive pattern.

2. The interconnection structure of the semiconductor integrated circuit device of claim 1, wherein the first length is longer than the second length.

3. The interconnection structure of the semiconductor integrated circuit device of claim 2, wherein the first width is substantially the same as the second width.

4. The interconnection structure of the semiconductor integrated circuit device of claim 1, wherein the first width is wider than the second width.

5. The interconnection structure of the semiconductor integrated circuit device of claim 4, wherein the first length is substantially the same as the second length.

6. The interconnection structure of the semiconductor integrated circuit device of claim 4, wherein the contact part is configured to make contact with a sidewall of the second conductive pattern and a portion of the first conductive pattern exposed through the second conductive pattern.

7. Interconnection structures of a semiconductor integrated circuit device comprising:

a first interconnection;

a second interconnection extended in parallel to the first interconnection; and

an insulating layer interposed between the first interconnection and the second interconnection,

wherein each of the first and second interconnection comprises a dielectric layer formed in the first and second interconnections and a capacitor connected to a coupling capacitor generated between the first interconnection and the second interconnection in series,

wherein each of the first and second interconnections comprises;

a first conductive pattern having a first width and a first length;

a second conductive pattern formed over the first conductive pattern, the second conductive pattern having a second width substantially the same as the first width and a second length shorter than the first length; and

a dielectric layer interposed between the first conductive pattern and the second conductive pattern,

wherein each of the interconnection structures, respectively, further comprise;

a contact part configured to simultaneously make contact with the first conductive pattern and the second conductive pattern, and

wherein the second conductive patterns are, respectively, configured to expose an edge portions of the first conductive pattern, and the contact parts are, respectively, configured to make contact with an edge portion of the second conductive pattern and the exposed edge portion of the first conductive pattern.

8. The interconnection structures of the semiconductor integrated circuit device of claim 7,

wherein each of the first and second interconnections comprises:

a first conductive pattern having a first width and a first length;

a second conductive pattern arranged over the first conductive pattern, the second conductive pattern having a second width narrower than the first width and a second length substantially the same as the first length; and

a dielectric layer interposed between the first conductive pattern and the second conductive pattern; and

wherein each of the interconnection structures, respectively, further comprise;

a contact part configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.

9. The interconnection structures of the semiconductor integrated circuit device of claim 8, wherein the contact parts are, respectively, configured to make contact with a sidewall of the second conductive pattern and a portion of the first conductive pattern exposed through the second conductive pattern.

10. The interconnection structures of the semiconductor integrated circuit device of claim 8, wherein the first conductive pattern in the first interconnection is spaced apart from the first conductive pattern in the second interconnection by a first gap, and the second conductive pattern in the first interconnection is spaced apart from the second conductive pattern in the second interconnection by a second gap wider than the first gap.