Substrate-less stackable package with wire-bond interconnect

• US 10,170,412 B2
• Filed: 04/12/2018
• Issued: 01/01/2019
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Mohammed, Ilyas
• Primary Examiner(s): Armand, Marc
• Application Number:
  US15/951,925
• Publication Number:
  US 20180233448A1
• Time in Patent Office: 264 Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45155 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/45565 Single coating layer
• CPC Class Codes: H01L 2224/45624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45655 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/45664 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/45669 Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/4569 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/48 : of an individual wire connector
• CPC Class Codes: H01L 2224/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/182 : Disposition
• CPC Class Codes: H01L 2924/191 : Disposition
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H05K 2201/10287 : Metal wires as connectors or conductors
• CPC Class Codes: H05K 2203/1461 : Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
• CPC Class Codes: H05K 3/4046 : using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Abstract

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

Claims

1. An apparatus, comprising:

conductive elements of a conductive layer on a bottom side of a package;

wire bond wires coupled to and extending from first upper surface portions of the conductive elements;

a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;

a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; and

a dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.

2. The apparatus according to claim 1, wherein the redistribution is configured to provide contacts of the package for interconnects for electrical conductivity with a microelectronic structure.

3. The apparatus according to claim 1, wherein the redistribution is a lower redistribution, the apparatus further comprising a redistribution layer on an upper surface of dielectric layer interconnected for electrical conductivity to the wire bond wires for an upper redistribution on a top side of the package.

4. The apparatus according to claim 3, wherein the lower redistribution and the upper redistribution respectively are configured for providing contacts of the package for interconnects for electrical conductivity with a first microelectronic structure and a second microelectronic structure.

5. The apparatus according to claim 4, wherein the microelectronic element is in a face-down orientation.

6. The apparatus according to claim 4, wherein the conductive elements are patterned from the conductive layer to define shapes of the conductive elements.

7. The apparatus according to claim 4, wherein the wire bond wires are spaced away from a perimeter of the microelectronic element for the lower redistribution.

8. The apparatus according to claim 7, wherein the redistribution layer extends over a backside surface of the microelectronic element for the upper redistribution.

9. The apparatus according to claim 8, wherein the conductive contact structure includes a pad of the microelectronic element.

10. The apparatus according to claim 9, wherein the conductive contact structure includes a solder mass.

11. The apparatus according to claim 10, wherein the conductive contact structure includes a metalized via including the solder mass.

12. The apparatus according to claim 7, wherein the conductive element is a trace.

13. The apparatus according to claim 3, wherein the microelectronic element and the conductive contact structures respectively are a first microelectronic element and first conductive contact structures, the apparatus further comprising:

a second microelectronic element in a face-up orientation coupled over the first microelectronic element; and

the redistribution layer extending over the second microelectronic element and interconnected for electrical conductivity to the second microelectronic element through second conductive contact structures.

14. The apparatus according to claim 13, wherein the second conductive contact structures include respective pads of the second microelectronic element.

15. The apparatus according to claim 14, wherein the second conductive contact structures include respective solder masses.

16. The apparatus according to claim 13, wherein the wire bond wires include coated cores.

17. The apparatus according to claim 3, wherein the microelectronic element includes a first microelectronic element and a second microelectronic element in a stack.

18. The apparatus according to claim 17, wherein the conductive contact structures are first conductive contact structures, the apparatus further comprising:

second conductive contact structures interconnected for electrical conductivity between the redistribution layer and the second microelectronic element.

19. The apparatus according to claim 18, wherein:

the first microelectronic element is in a face-down orientation in the stack;

the second microelectronic element is in a face-up orientation and above the first microelectronic element in the stack; and

the redistribution layer extends over the second microelectronic element and is interconnected for electrical conductivity between the redistribution layer and the second microelectronic element through the second conductive contact structures.

20. The apparatus according to claim 19, wherein the first and the second conductive contact structures include respective pads respectively of the first and the second microelectronic element.